利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.032 秒)

    Method for reducing contact resistance of CMOS image sensor
    1.
    发明授权
    Method for reducing contact resistance of CMOS image sensor 有权
    降低CMOS图像传感器接触电阻的方法

    公开(公告)号：US08247262B2

    公开(公告)日：2012-08-21

    申请号：US12772539

    申请日：2010-05-03

    申请人： Kuan-Chieh Huang ,  Chih-Jen Wu ,  Chen-Ming Huang ,  Dun-Nian Yaung ,  An-Chun Tu

    发明人： Kuan-Chieh Huang ,  Chih-Jen Wu ,  Chen-Ming Huang ,  Dun-Nian Yaung ,  An-Chun Tu

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14689 ,  H01L21/28518

    摘要： A method for performing a CMOS Image Sensor (CIS) silicide process is provided to reduce pixel contact resistance. In one embodiment, the method comprises forming a Resist Protect Oxide (RPO) layer on the CIS, forming a Contact Etch Stop Layer (CESL), forming an Inter-Layer Dielectric (ILD) layer, performing contact lithography/etching, performing Physical Vapor Deposition (PVD) at a pixel contact hole area, annealing for silicide formation at pixel contact hole area, performing contact filling, and defining the first metal layer. The Resist Protect Oxide (RPO) layer can be formed without using a photo mask of Cell Resist Protect Oxide (CIRPO) photolithography for pixel array and/or without silicide process at pixel array. The method can include implanting N+ or P+ for pixel contact plugs at the pixel contact hole area. The contact filling can comprise depositing contact glue plugs and performing Chemical Mechanical Polishing (CMP).

    摘要翻译： 提供了用于执行CMOS图像传感器（CIS）硅化物处理的方法以减少像素接触电阻。 在一个实施例中，该方法包括在CIS上形成抗蚀保护氧化物（RPO）层，形成接触蚀刻停止层（CESL），形成层间介电层（ILD）层，进行接触光刻/蚀刻，进行物理蒸气 在像素接触孔区域沉积（PVD），在像素接触孔区域进行硅化物形成退火，进行接触填充和限定第一金属层。 可以形成抗蚀保护氧化物（RPO）层，而不使用用于像素阵列的和/或不在像素阵列处的硅化物处理的电池抗蚀保护氧化物（CIRPO）光刻的光掩模。 该方法可以包括在像素接触孔区域处植入用于像素接触插塞的N +或P +。 接触填充可以包括沉积接触胶塞并进行化学机械抛光（CMP）。

    Method for reducing contact resistance of CMOS image sensor
    2.
    发明授权
    Method for reducing contact resistance of CMOS image sensor 有权
    降低CMOS图像传感器接触电阻的方法

    公开(公告)号：US08586404B2

    公开(公告)日：2013-11-19

    申请号：US13556869

    申请日：2012-07-24

    申请人： Kuan-Chieh Huang ,  Chih-Jen Wu ,  Chen-Ming Huang ,  Dun-Nian Yaung ,  An-Chun Tu

    发明人： Kuan-Chieh Huang ,  Chih-Jen Wu ,  Chen-Ming Huang ,  Dun-Nian Yaung ,  An-Chun Tu

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14689 ,  H01L21/28518

    摘要： This description relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes performing Physical Vapor Deposition (PVD) at a pixel contact hole area, annealing for silicide formation at the pixel contact hole area and performing contact filling. This description also relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes implanting N+ or P+ for pixel contact plugs at a pixel contact hole area, performing Physical Vapor Deposition (PVD) at pixel contact hole area, annealing for silicide formation at the pixel contact hole area, performing contact filling and depositing a first metal film layer, wherein the first metal film layer links contact holes for a source, a drain, or a poly gate of a CMOS device.

    摘要翻译： 本说明书涉及用于降低CMOS图像传感器（CIS）接触电阻的方法，CIS具有像素阵列和周边。 该方法包括在像素接触孔区域进行物理气相沉积（PVD），在像素接触孔区域进行硅化物形成退火并进行接触填充。 该描述还涉及用于减小CMOS图像传感器（CIS）接触电阻的方法，CIS具有像素阵列和周边。 该方法包括在像素接触孔区域处对像素接触插塞注入N +或P +，在像素接触孔区域进行物理气相沉积（PVD），在像素接触孔区域进行硅化物形成退火，执行接触填充和沉积第一金属 膜层，其中所述第一金属膜层连接CMOS器件的源极，漏极或多晶硅栅极的接触孔。

    Semiconductor Test Structures
    6.
    发明申请
    Semiconductor Test Structures 有权
    半导体测试结构

    公开(公告)号：US20140203282A1

    公开(公告)日：2014-07-24

    申请号：US14246529

    申请日：2014-04-07

    申请人： An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    发明人： An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2644 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes.

    摘要翻译： 一种使用电阻器件执行的方法，其中所述电阻器件包括具有通过栅电极的最长尺寸的电介质和电触点与栅电极分离的有源区的衬底，所述方法包括执行一个或多个工艺以形成 电阻器件，测量电触点之间的电阻，并将所测量的电阻与一个或多个过程中的变化相关联。

    Semiconductor Test Structures
    7.
    发明申请
    Semiconductor Test Structures 有权
    半导体测试结构

    公开(公告)号：US20130076385A1

    公开(公告)日：2013-03-28

    申请号：US13241634

    申请日：2011-09-23

    申请人： An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    发明人： An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    IPC分类号： G01R1/067

    CPC分类号： G01R31/2644 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.

    摘要翻译： 一种电阻测试结构，其包括具有有源区的半导体衬底，形成在有源区上的栅极叠层，与栅极堆叠的相对侧上的有源区连通的第一电触点，第一电触点提供跨越 栅极堆叠的第一尺寸和与栅极堆叠的相对侧上的有源区域连通的第二电触点，第二电触点跨过栅极堆叠的第一维度提供电短路，第一和第二电极 接触件沿垂直于第一尺寸的栅极堆叠的第二尺寸间隔开。

    Semiconductor test structures
    8.
    发明授权
    Semiconductor test structures 有权
    半导体测试结构

    公开(公告)号：US08704224B2

    公开(公告)日：2014-04-22

    申请号：US13241634

    申请日：2011-09-23

    申请人： An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    发明人： An-Chun Tu ,  Chen-Ming Huang ,  Chih-Jen Wu ,  Chin-Hsiang Lin

    IPC分类号： H01L23/10

    CPC分类号： G01R31/2644 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.

    摘要翻译： 一种电阻测试结构，其包括具有有源区的半导体衬底，形成在有源区上的栅极叠层，与栅极堆叠的相对侧上的有源区连通的第一电触点，第一电触点提供跨越 栅极堆叠的第一尺寸和与栅极堆叠的相对侧上的有源区域连通的第二电触点，第二电触点跨过栅极堆叠的第一维度提供电短路，第一和第二电极 接触件沿垂直于第一尺寸的栅极堆叠的第二尺寸间隔开。

    Advanced process control for gate profile control
    9.
    发明授权
    Advanced process control for gate profile control 有权
    门型材控制的先进过程控制

    公开(公告)号：US08352062B2

    公开(公告)日：2013-01-08

    申请号：US12402124

    申请日：2009-03-11

    申请人： Chih-Jen Wu ,  Chen-Ming Huang ,  An-Chun Tu

    发明人： Chih-Jen Wu ,  Chen-Ming Huang ,  An-Chun Tu

    IPC分类号： G06F19/00

    CPC分类号： H01L21/28026 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; performing a plurality of processes to form a gate stack over the substrate, wherein the gate stack comprises a gate layer; measuring a grain size of the gate layer after at least one of the plurality of processes; determining whether the measured grain size is within a target range; and modifying a recipe of at least one of the plurality of processes if the measured grain size of the gate layer is not within the target range.

    摘要翻译： 公开了一种制造具有改进性能的集成电路的方法。 该方法包括提供基底; 执行多个处理以在所述衬底上形成栅极堆叠，其中所述栅极堆叠包括栅极层; 在所述多个处理中的至少一个处理之后测量所述栅极层的晶粒尺寸; 确定所测量的晶粒尺寸是否在目标范围内; 以及如果所述测量的所述栅极层的晶粒尺寸不在所述目标范围内，则修改所述多个处理中的至少一个处理的配方。

    ADVANCED PROCESS CONTROL FOR GATE PROFILE CONTROL
    10.
    发明申请
    ADVANCED PROCESS CONTROL FOR GATE PROFILE CONTROL 有权
    门控轮廓控制的先进过程控制

    公开(公告)号：US20100234975A1

    公开(公告)日：2010-09-16

    申请号：US12402124

    申请日：2009-03-11

    申请人： Chih-Jen Wu ,  Chen-Ming Huang ,  An-Chun Tu

    发明人： Chih-Jen Wu ,  Chen-Ming Huang ,  An-Chun Tu

    IPC分类号： G05B13/02 ,  G06F17/00

    CPC分类号： H01L21/28026 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; performing a plurality of processes to form a gate stack over the substrate, wherein the gate stack comprises a gate layer; measuring a grain size of the gate layer after at least one of the plurality of processes; determining whether the measured grain size is within a target range; and modifying a recipe of at least one of the plurality of processes if the measured grain size of the gate layer is not within the target range.

    摘要翻译： 公开了一种制造具有改进性能的集成电路的方法。 该方法包括提供基底; 执行多个处理以在所述衬底上形成栅极堆叠，其中所述栅极堆叠包括栅极层; 在所述多个处理中的至少一个处理之后测量所述栅极层的晶粒尺寸; 确定所测量的晶粒尺寸是否在目标范围内; 以及如果所述测量的所述栅极层的晶粒尺寸不在所述目标范围内，则修改所述多个处理中的至少一个处理的配方。