公开(公告)号：US08705289B2

公开(公告)日：2014-04-22

申请号：US13344621

申请日：2012-01-06

申请人： Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ming Ku ,  Yung-Hsiang Chen ,  Shih-Chen Wang ,  Hsin-Ming Chen

发明人： Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ming Ku ,  Yung-Hsiang Chen ,  Shih-Chen Wang ,  Hsin-Ming Chen

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C16/12

摘要： A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.

摘要翻译： 提供一种闪存装置。 闪存装置包括多个存储单元和多个编程电压控制发生器。 每个存储单元通过其控制端接收编程控制电压，并根据编程控制电压执行数据编程操作。 每个编程电压控制发生器包括预充电电压发射器和泵浦电容器。 预充电电压发射器在第一时段期间根据预充电使能信号向每个相应存储器单元的末端提供预充电电压。 在第二时段期间向泵浦电容器提供泵浦电压，并且在每个存储器单元的控制端产生编程控制电压。

公开(公告)号：US08638589B2

公开(公告)日：2014-01-28

申请号：US13366370

申请日：2012-02-06

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C16/04 ,  H01L29/788 ,  H01L29/66 ,  H01L23/52

CPC分类号： H01L21/28282 ,  G11C16/10 ,  H01L27/11206 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.

摘要翻译： 提供了一种用于存储单元的操作方法，其中存储单元包括阱区，选择栅极，第一栅极，第二栅极，氧化物氮化物间隔物，第一扩散区域和第二扩散区域。 存储单元的操作方法包括以下步骤。 在编程操作期间，击穿电压通过形成在选择栅极下方的第一沟道区域耦合到第二扩散区域。 编程电压被顺序地或同时地施加到第一栅极和第二栅极以破裂第一氧化物层和第二氧化物层，其中第一氧化物层设置在第一栅极和阱区域之间，第二氧化物层是 设置在第二栅极和阱区域之间。

公开(公告)号：US08625350B2

公开(公告)日：2014-01-07

申请号：US13485920

申请日：2012-06-01

申请人： Wen-Hao Ching ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Wen-Hao Ching ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： G11C16/0441 ,  G11C2216/10 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

摘要翻译： 非易失性存储器系统包括一个或多个非易失性存储器单元。 每个非易失性存储单元提供浮动栅极，耦合器件，第一浮栅晶体管和第二浮栅晶体管。 耦合装置位于第一导电区域中。 第一浮栅晶体管位于第二导电区域中，并提供在读操作期间感测到的读电流。 第二浮栅晶体管位于第三导电区域中。 这种非易失性存储单元进一步提供两个晶体管，用于在编程操作期间将负电荷注入浮置栅极，以及在擦除操作期间从第二浮栅晶体管去除负电荷。 浮置栅极由第一浮栅晶体管，耦合器件和第二浮栅晶体管共享，并且延伸在第一浮栅晶体管，耦合器件和第二浮栅晶体管的有源区上。

公开(公告)号：US08497172B2

公开(公告)日：2013-07-30

申请号：US13549525

申请日：2012-07-16

申请人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Shih-Jye Shen

发明人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Shih-Jye Shen

IPC分类号： H01L21/336

CPC分类号： H01L27/112 ,  G11C17/12 ,  H01L27/1126

摘要： A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.

摘要翻译： 掩模定义的只读存储器阵列形成在衬底上，并且包括具有相反极性的第一ROM位和第二ROM位。 第一ROM位具有形成在衬底的第一区域上的第一MOS晶体管和第一阻挡层。 第一MOS晶体管的第二源极/漏极区域和第一扩散区域形成在第一块层的相对侧上的衬底的第一区域中。 第二ROM位包括第二MOS晶体管。

公开(公告)号：US08466519B2

公开(公告)日：2013-06-18

申请号：US12536506

申请日：2009-08-06

申请人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Shih-Jye Shen

发明人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Shih-Jye Shen

IPC分类号： H01L27/112 ,  H01L21/336

CPC分类号： H01L27/112 ,  G11C17/12 ,  H01L27/1126

摘要： A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.

摘要翻译： 掩模定义的只读存储器阵列形成在衬底上，并且包括具有相反极性的第一ROM位和第二ROM位。 第一ROM位具有形成在衬底的第一区域上的第一MOS晶体管和第一阻挡层。 第一MOS晶体管的第二源极/漏极区域和第一扩散区域形成在第一块层的相对侧上的衬底的第一区域中。 第二ROM位包括第二MOS晶体管。

公开(公告)号：US08390056B2

公开(公告)日：2013-03-05

申请号：US13253083

申请日：2011-10-05

申请人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344

摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.

摘要翻译： 非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。 第一区域和第二区域被分开足以在其间形成自对准电荷存储层的距离。

公开(公告)号：US20120273860A1

公开(公告)日：2012-11-01

申请号：US13541755

申请日：2012-07-04

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

IPC分类号： H01L27/06

CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.

摘要翻译： 唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。 第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。 第二耦合电容器的一端连接到第二晶体管的栅极并耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

公开(公告)号：US08199578B2

公开(公告)日：2012-06-12

申请号：US12792746

申请日：2010-06-03

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Ching-Sung Yang

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L27/11558 ,  G11C16/0433 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.

摘要翻译： 提供具有浮置栅晶体管，编程门和控制栅极的单多晶硅层非易失性存储器。 浮栅晶体管具有浮置栅极和隧穿介电层。 浮栅设置在基板上。 隧道介电层设置在浮置栅极和衬底之间。 编程栅极，控制栅极和擦除栅极分别设置在由隧道电介质层分离的浮置栅极下的衬底中。 因此，在编程操作和擦除操作期间，通过隧道介电层的不同区域注入和排出电荷，以增加非易失性存储器的可靠性。

公开(公告)号：US07937072B2

公开(公告)日：2011-05-03

申请号：US12342082

申请日：2008-12-23

申请人： Tung-Cheng Kuo ,  Ching-Sung Yang ,  Ruei-Ling Lin ,  Cheng-Jye Liu

发明人： Tung-Cheng Kuo ,  Ching-Sung Yang ,  Ruei-Ling Lin ,  Cheng-Jye Liu

IPC分类号： H04M1/66 ,  H04M3/16 ,  H04M1/68

CPC分类号： H04W12/08 ,  G06F21/44 ,  H04W12/12 ,  H04W88/02

摘要： The present invention provides a mobile phone accessing system. The mobile phone accessing system comprises: a mobile phone having a first International Mobile Equipment Identity (IMEI) code; and a storage device comprising a first storage region for storing data, a second storage region for storing a second IMEI code, and a controller coupled to the first storage region and the second storage region for executing a security check function to determine whether the mobile phone is qualified to access the first storage region according to the first IMEI code.

摘要翻译： 本发明提供一种移动电话接入系统。 移动电话接入系统包括：具有第一国际移动设备标识（IMEI）码的移动电话; 以及存储装置，包括用于存储数据的第一存储区域，用于存储第二IMEI代码的第二存储区域和耦合到第一存储区域和第二存储区域的控制器，用于执行安全检查功能以确定移动电话 有资格根据第一个IMEI代码访问第一个存储区域。

公开(公告)号：US20110024823A1

公开(公告)日：2011-02-03

申请号：US12633780

申请日：2009-12-08

申请人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344

摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.

摘要翻译： 非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。 第一区域和第二区域被分开足以在其间形成自对准电荷存储层的距离。