公开(公告)号：US20090117723A1

公开(公告)日：2009-05-07

申请号：US12287945

申请日：2008-10-15

申请人： Jong-Kyu Kim ,  Bum-Soo Kim ,  Jong-Heui Song ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Kuk-Han Yoon

发明人： Jong-Kyu Kim ,  Bum-Soo Kim ,  Jong-Heui Song ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Kuk-Han Yoon

IPC分类号： H01L21/28 ,  H01L21/283

CPC分类号： H01L29/42324 ,  H01L21/02071 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/32139 ,  H01L27/11521 ,  H01L29/40114

摘要： In a method of forming a conductive pattern in a semiconductor device, a conductive layer including a metal is formed on a substrate. A mask including carbon is provided on the conductive layer, and the conductive pattern is formed on the substrate by etching the conductive layer using the mask as an etching mask. The mask is removed from the conductive pattern by an oxygen plasma ashing process. An oxidized portion of the conductive pattern is reduced. The conductive pattern may have a desired resistance by reducing the oxidized portion to improve electrical characteristics and reliability of the semiconductor device.

摘要翻译： 在半导体器件中形成导电图案的方法中，在衬底上形成包括金属的导电层。 在导电层上设置包含碳的掩模，并且通过使用掩模作为蚀刻掩模蚀刻导电层，在基板上形成导电图案。 通过氧等离子体灰化处理将掩模从导电图案中去除。 导电图案的氧化部分减少。 导电图案可以通过减少氧化部分而具有期望的电阻，以改善半导体器件的电特性和可靠性。

公开(公告)号：US20060046382A1

公开(公告)日：2006-03-02

申请号：US11206418

申请日：2005-08-17

申请人： Kuk-Han Yoon ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Jong-Kyu Kim

发明人： Kuk-Han Yoon ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Jong-Kyu Kim

IPC分类号： H01L21/8242

CPC分类号： H01L27/10817 ,  H01L27/10852 ,  H01L28/91

摘要： In an embodiment, a method of forming a capacitor for a semiconductor device of which structural stability is improved is shown. Cylindrical storage electrodes are formed in a matrix pattern on a substrate that includes an insulation interlayer having contacts therein so that a mold layer surrounds the cylindrical storage electrodes. Sacrificial plugs are formed with a cap within these electrodes. A stabilizing layer is formed on the etched mold layer and the cylindrical storage electrode by partially etching the mold layer. The stabilizing layer is etched until the sacrificial plug is exposed, thereby forming a spacer. While the sacrificial plug and the mold layer are fully removed, the spacer is partially removed, thereby forming a stabilizing member for supporting neighboring storage electrodes adjacent to each other. Accordingly, a structural stability of the capacitor is improved.

摘要翻译： 在一个实施例中，示出了形成其结构稳定性提高的半导体器件的电容器的方法。 圆柱形存储电极在基板上以矩阵图案形成，该基板包括其中具有触点的绝缘中间层，使得模具层围绕圆柱形存储电极。 牺牲塞在这些电极内形成有盖。 通过部分蚀刻模具层，在蚀刻的模具层和圆柱形存储电极上形成稳定层。 蚀刻稳定层，直到牺牲塞被暴露，从而形成间隔物。 尽管完全去除了牺牲塞和模具层，但是间隔件被部分地移除，从而形成用于支撑彼此相邻的相邻存储电极的稳定构件。 因此，提高了电容器的结构稳定性。

公开(公告)号：US08704283B2

公开(公告)日：2014-04-22

申请号：US12724450

申请日：2010-03-16

申请人： Jong-Kyu Kim ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Heung-Sik Park ,  Kuk-Han Yoon ,  Yong-Joon Choi

发明人： Jong-Kyu Kim ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Heung-Sik Park ,  Kuk-Han Yoon ,  Yong-Joon Choi

IPC分类号： H01L27/108

CPC分类号： H01L27/10852 ,  H01L28/91

摘要： A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.

摘要翻译： 半导体器件包括下电极，至少包围下电极的上部的支撑构件，下电极上的电介质层和支撑构件，以及设置在电介质层上的上电极。 支撑构件可以具有在下电极的侧壁的上部上延伸的第一部分和覆盖下电极的上表面的第二部分。 支撑构件的第一部分突出在下电极的上方。

公开(公告)号：US20080096378A1

公开(公告)日：2008-04-24

申请号：US11711118

申请日：2007-02-27

申请人： Jong-Kyu Kim ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Kuk-Han Yoon ,  Bum-Soo Kim

发明人： Jong-Kyu Kim ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Kuk-Han Yoon ,  Bum-Soo Kim

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/11521

摘要： In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.

摘要翻译： 在形成接触结构的方法中，第一和第二导电结构可以形成在下部结构上以彼此间隔开。 可以在下部结构上形成绝缘层以覆盖第一和第二导电结构。 露出第一导电结构的第一孔可以通过绝缘层形成。 间隔件可以形成在第一孔的侧壁上。 电耦合到第一导电结构的第一触点可以形成在具有形成间隔件的侧壁的第一孔中。 可以去除位于间隔物之间​​的绝缘层的一部分，以形成暴露第二导电结构的第二孔。 电耦合到第二导电结构的第二触点可以形成在第二孔中。

公开(公告)号：US20100237466A1

公开(公告)日：2010-09-23

申请号：US12724450

申请日：2010-03-16

申请人： Jong-Kyu Kim ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Heung-Sik Park ,  Kuk-Han Yoon ,  Yong-Joon Choi

发明人： Jong-Kyu Kim ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Heung-Sik Park ,  Kuk-Han Yoon ,  Yong-Joon Choi

IPC分类号： H01L29/92

CPC分类号： H01L27/10852 ,  H01L28/91

摘要： A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.

摘要翻译： 半导体器件包括下电极，至少包围下电极的上部的支撑构件，下电极上的电介质层和支撑构件，以及设置在电介质层上的上电极。 支撑构件可以具有在下电极的侧壁的上部上延伸的第一部分和覆盖下电极的上表面的第二部分。 支撑构件的第一部分突出在下电极的上方。

公开(公告)号：US07557026B2

公开(公告)日：2009-07-07

申请号：US11711118

申请日：2007-02-27

申请人： Jong-Kyu Kim ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Kuk-Han Yoon ,  Bum-Soo Kim

发明人： Jong-Kyu Kim ,  Sang-Sup Jeong ,  Sung-Gil Choi ,  Kuk-Han Yoon ,  Bum-Soo Kim

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/11521

摘要： In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.

摘要翻译： 在形成接触结构的方法中，第一和第二导电结构可以形成在下部结构上以彼此间隔开。 可以在下部结构上形成绝缘层以覆盖第一和第二导电结构。 露出第一导电结构的第一孔可以通过绝缘层形成。 间隔件可以形成在第一孔的侧壁上。 电耦合到第一导电结构的第一触点可以形成在具有形成间隔件的侧壁的第一孔中。 可以去除位于间隔物之间​​的绝缘层的一部分，以形成暴露第二导电结构的第二孔。 电耦合到第二导电结构的第二触点可以形成在第二孔中。

公开(公告)号：US07161205B2

公开(公告)日：2007-01-09

申请号：US10992963

申请日：2004-11-18

申请人： Sung-Gil Choi ,  Sang-Sup Jeong

发明人： Sung-Gil Choi ,  Sang-Sup Jeong

IPC分类号： H01L29/72

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： There are provided a semiconductor memory device including a cylindrical storage electrode and a method of manufacturing the same. The semiconductor memory device includes an interlevel dielectric layer with storage contact plugs formed on a semiconductor substrate. Cylindrical storage electrodes are formed above the interlevel dielectric layer and are electrically connected to the storage contact plugs. A spacer is coupled to a predetermined portion of the outer wall of the storage electrodes. A dielectric layer is formed on the storage electrode and on the spacer, and a plate electrode is formed above the dielectric layer. Accordingly, leaning and bit fail of the storage electrode are prevented.

摘要翻译： 提供一种包括圆柱形存储电极的半导体存储器件及其制造方法。 半导体存储器件包括形成在半导体衬底上的存储接触插塞的层间电介质层。 圆柱形存储电极形成在层间电介质层之上，并且电连接到存储触点。 间隔件联接到存储电极的外壁的预定部分。 在存储电极和间隔物上形成电介质层，在电介质层的上方形成平板电极。 因此，防止了存储电极的倾斜和位故障。

公开(公告)号：US06451663B1

公开(公告)日：2002-09-17

申请号：US09983348

申请日：2001-10-24

申请人： Sung-Gil Choi ,  Tae Hyuk Ahn ,  Sang Sup Jeong ,  Dae Hyuk Chung ,  Won Jun Lee

发明人： Sung-Gil Choi ,  Tae Hyuk Ahn ,  Sang Sup Jeong ,  Dae Hyuk Chung ,  Won Jun Lee

IPC分类号： H01L2120

CPC分类号： H01L28/91 ,  H01L21/3212 ,  Y10S438/949

摘要： A method of manufacturing a cylindrical storage node in a semiconductor device, in which loss differences of the cylindrical storage node between the center and the edge of cell areas, caused by an etch-back process of storage node isolation, is minimized, thereby maintaining uniform electrical capacitances over the entire area of a semiconductor wafer.

摘要翻译： 一种制造半导体器件中的圆柱形存储节点的方法，其中由存储节点隔离的回蚀处理引起的在单元区域的中心和边缘之间的圆柱形存储节点的损耗差最小化，从而保持均匀 在半导体晶片的整个区域上的电容。

公开(公告)号：US20050167724A1

公开(公告)日：2005-08-04

申请号：US10992963

申请日：2004-11-18

申请人： Sung-Gil Choi ,  Sang-Sup Jeong

发明人： Sung-Gil Choi ,  Sang-Sup Jeong

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L29/94 ,  H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： There are provided a semiconductor memory device including a cylindrical storage electrode and a method of manufacturing the same. The semiconductor memory device includes an interlevel dielectric layer with storage contact plugs formed on a semiconductor substrate. Cylindrical storage electrodes are formed above the interlevel dielectric layer and are electrically connected to the storage contact plugs. A spacer is coupled to a predetermined portion of the outer wall of the storage electrodes. A dielectric layer is formed on the storage electrode and on the spacer, and a plate electrode is formed above the dielectric layer. Accordingly, leaning and bit fail of the storage electrode are prevented.

摘要翻译： 提供一种包括圆柱形存储电极的半导体存储器件及其制造方法。 半导体存储器件包括形成在半导体衬底上的存储接触插塞的层间电介质层。 圆柱形存储电极形成在层间电介质层之上，并且电连接到存储触点。 间隔件联接到存储电极的外壁的预定部分。 在存储电极和间隔物上形成电介质层，在电介质层的上方形成平板电极。 因此，防止了存储电极的倾斜和位故障。

公开(公告)号：US20060289899A1

公开(公告)日：2006-12-28

申请号：US11447944

申请日：2006-06-07

申请人： Hyun-Chul Yoon ,  Jong-Kyu Kim ,  Jang-Bin Yim ,  Sang-Dong Kwon ,  Sung-Gil Choi

发明人： Hyun-Chul Yoon ,  Jong-Kyu Kim ,  Jang-Bin Yim ,  Sang-Dong Kwon ,  Sung-Gil Choi

IPC分类号： H01L27/10 ,  H01L21/82

CPC分类号： H01L27/101 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.