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公开(公告)号：US5008886A
公开(公告)日：1991-04-16
申请号：US303621
申请日：1989-01-27
CPC分类号： G06F11/1056
摘要： A method and apparatus for a read-modify-write operation in a digital computer memory system which reduces memory data path buffer storage requirements with a procedure which includes latching new write data and associated mask fields into a data output buffer and then merging read data with the new data in the output buffer according to the latched mask fields.
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2.发明授权Method and apparatus for reducing buffer storage in a read-modify-write operation 失效用于在读 - 修改 - 写操作中减少缓冲存储的方法和装置
公开(公告)号：US5235693A
公开(公告)日：1993-08-10
申请号：US582475
申请日：1990-09-14
CPC分类号： G06F11/1056
摘要： A method and apparatus for a read-modify-write operation in a digital computer memory system that reduces memory data path buffer storage requirements. The method latches new write data and associated mask fields into a data output buffer and then uses the latched mask fields to merge read data with the new data in the output buffer. The mask fields determine which portion of the read data is to be replaced with new data. Appropriate check bits for an error correction code (ECC) are generated and added to the modified data in the output buffer to produce a new data output which is released from the output buffer into the memory at the selected address.
摘要翻译： 一种用于在数字计算机存储器系统中进行读 - 修改 - 写入操作的方法和装置，其减少了存储器数据路径缓冲器存储要求。 该方法将新的写入数据和相关的掩码字段锁存到数据输出缓冲区中，然后使用锁存的掩码字段将读取的数据与输出缓冲区中的新数据进行合并。 掩码字段确定要用新数据替换读取数据的哪一部分。 生成用于纠错码（ECC）的适当的校验位并将其添加到输出缓冲器中的修改数据，以产生从输出缓冲器释放到选定地址的存储器中的新数据输出。
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3.发明授权Method and apparatus for reducing memory read latency in a shared memory system with multiple processors 失效用于在具有多个处理器的共享存储器系统中减少存储器读取延迟的方法和装置
公开(公告)号：US5185875A
公开(公告)日：1993-02-09
申请号：US302839
申请日：1989-01-27
CPC分类号： G06F12/0817
摘要： Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles include a first dual operation mode which confirms that the transferred data is the most current and then concurrently writes the CPU transferred data into the SCU main memory while transferring it directly to the requesting CPU, and a second dual operation mode which confirms that only a portion of the transferred data is the most current and then concurrently writes the portion of the transferred data that is most current in the SCU memory and reads the written data that is most current in the SCU memory and reads the written data for transfer to the requesting CPU.
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公开(公告)号：US5255381A
公开(公告)日：1993-10-19
申请号：US582476
申请日：1990-09-14
申请人： Kumar Chinnaswamy , Hansel A. Collins , Michael B. Evans , Timothy P. Fissette , Michael A. Gagliardo , John J. Lynch , James E. Tessari
发明人： Kumar Chinnaswamy , Hansel A. Collins , Michael B. Evans , Timothy P. Fissette , Michael A. Gagliardo , John J. Lynch , James E. Tessari
IPC分类号： G06F11/22 , G01R31/317 , G06F11/273 , G06F12/16 , G11C11/4076 , G06F12/00 , G11C7/00
CPC分类号： G11C11/4076 , G01R31/31701 , G06F11/2736
摘要： Methods and apparatus for immunizing dynamic random access memory (DRAM) modules in the data processing system against data loss from transitions that occur with memory mode switching during the scan operation and permitting normal operations to be performed on the memory modules regardless of the state of the system clocks.
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公开(公告)号：US5371874A
公开(公告)日：1994-12-06
申请号：US105101
申请日：1993-08-09
CPC分类号： G06F12/0817
摘要： Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles include a first dual operation mode which confirms that the transferred data is the most current and then concurrently write the CPU transferred data into the SCU main memory while transferring it directly to the requesting CPU, and a second dual operation mode which confirms that only a portion of the transferred data is the most current and then concurrently write the portion of the transferred data that is most current in the SCU memory and read the written data for transfer to the requesting CPU.
摘要翻译： 用于减少由一个中央处理单元（CPU）请求的选定数据的内存读取延迟并通过具有特殊数据传输周期的系统控制单元（SCU）从另一个CPU检索的存储器读取等待时间的方法和装置。 特殊数据传输周期包括第一双重操作模式，其确认传送的数据是最新的，然后在将CPU传送的数据直接传送到请求的CPU的同时将CPU传送的数据同时写入SCU主存储器中，并且将第二双重操作模式 确认只有一部分传输的数据是最新的，然后同时写入SCU存储器中最新的传送数据的部分，并读取写入的数据以传送到请求CPU。
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6.发明授权Method and apparatus for performing diagnosis scanning of a memory unit regardless of the state of the system clock and without affecting the store data 失效无论系统时钟的状态如何而不影响存储数据，执行存储器单元的诊断扫描的方法和装置
公开(公告)号：US5313623A
公开(公告)日：1994-05-17
申请号：US547656
申请日：1990-07-03
申请人： Kumar Chinnaswamy , Hansel A. Collins , Michael B. Evans , Timothy P. Fissette , Michael A. Gagliardo , John J. Lynch , James E. Tessari
发明人： Kumar Chinnaswamy , Hansel A. Collins , Michael B. Evans , Timothy P. Fissette , Michael A. Gagliardo , John J. Lynch , James E. Tessari
IPC分类号： G01R31/317 , G06F11/273 , G11C11/4076 , G06F11/22
CPC分类号： G01R31/31701 , G11C11/4076 , G06F11/2736
摘要： Methods and apparatus for immunizing dynamic random access memory (DRAM) modules in the data processing system against data loss from transitions that occur with memory mode switching during the scan operation and permitting normal operations to be performed on the memory modules regardless of the state of the system clocks.
摘要翻译： 用于免疫数据处理系统中的动态随机存取存储器（DRAM）模块的方法和装置，以防止在扫描操作期间随着存储器模式切换而发生的转换的数据丢失，并允许对存储器模块执行正常操作，而不管 系统时钟。
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7.发明授权Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory 失效用于与用于将多处理器系统的系统控制单元与系统主存储器连接的装置的存储器配置
公开(公告)号：US5043874A
公开(公告)日：1991-08-27
申请号：US306404
申请日：1989-02-03
IPC分类号： G06F15/16 , G06F12/06 , G06F13/16 , G06F15/167 , G06F15/177 , G06F15/80
CPC分类号： G06F13/1663 , G06F12/0607 , G06F15/8015
摘要： In a multi-processing computer system including a plurality of central processing units (CPUs) and input/output (I/O) units, a system memory including a plurality of DRAM-based memory segments, a system control unit (SCU) for operating the CPUs in a parallel fashion and allowing the CPUs and other system units to controllably access addressable segments of system memory, and an interface for establishing communication between the SCU and the system memory and regulating the transfer of memory commands and associated data therebetween, the system memory is configured in the form of at least one independently accessible memory unit having a first dedicated data path for the transfer of read data from addressed memory segments to the interface for transfer to the SCU, a second dedicated data path for transfer of write data received from the SCU through the interface to addressed memory segments, and a third dedicated path for transfer of addresses from the SCU to identify addressed segment of memory.
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8.发明授权System and process for high-availability, direct, flexible and scalable switching of data packets in broadband networks 有权高可用性，直接，灵活和可扩展的宽带网络中数据包交换的系统和流程公开(公告)号：US06826195B1
公开(公告)日：2004-11-30
申请号：US09474039
申请日：1999-12-28
申请人： Paul E. Nikolich , Kumar Chinnaswamy , Paul H. Dormitzer , Willem A. H. Engelse , Walter G. Mahla , Howard Ngai , David R. Paolino , Kirk B. Pearce , Jyotirmoy B. Sarkar
发明人： Paul E. Nikolich , Kumar Chinnaswamy , Paul H. Dormitzer , Willem A. H. Engelse , Walter G. Mahla , Howard Ngai , David R. Paolino , Kirk B. Pearce , Jyotirmoy B. Sarkar
IPC分类号： H04J322
CPC分类号： H04Q11/0478
摘要： A system and process for directly and flexibly switching connections of data packet flows between nodes of a broadband data processing system network. The system acts as a single IP switch.
摘要翻译： 一种用于在宽带数据处理系统网络的节点之间直接和灵活地切换数据分组流的连接的系统和过程。 该系统充当单个IP交换机。
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9.发明授权System having a meshed backplane and process for transferring data therethrough 有权具有网格背板的系统和用于传送数据的过程公开(公告)号：US06611526B1
公开(公告)日：2003-08-26
申请号：US09566540
申请日：2000-05-08
IPC分类号： H04L1228
CPC分类号： H04L12/6402
摘要： A meshed backplane has dedicated pairs of connections for high-speed serial connection in each direction between each of multiple application modules and each other application module. A management/control bus is provided for out-of-band signaling. The mesh of serial differential pairs may be used for management/control bus signals when necessary. A time division multiplexing fabric is also provided for telephony applications. A star interconnect region is provided for distribution of signals from redundant clocks.
摘要翻译： 网格背板具有用于在多个应用模块和每个其他应用模块中的每个方向上的高速串行连接的专用对连接。 为带外信令提供管理/控制总线。 串行差分对的网格可以在必要时用于管理/控制总线信号。 还为电话应用提供时分复用结构。 提供星形互连区域用于从冗余时钟分配信号。
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10.发明授权Modular crossbar interconnection metwork for data transactions between system units in a multi-processor system 失效用于多处理器系统中的系统单元之间的数据交易的模块化交叉开关互连功能
公开(公告)号：US4968977A
公开(公告)日：1990-11-06
申请号：US306336
申请日：1989-02-03
IPC分类号： H04Q3/555 , G06F13/40 , G06F15/173
CPC分类号： G06F15/17375 , G06F13/4022
摘要： For efficiently handling data transactions between various system units (CPUs, I/O units and main memory units) in a multi-processor system, the system units are linked via a plurality of expandable crossbar modules, each providing a set of interconnections or well-defined mappings between the sets of input and output nodes, with each output being defined in terms of only one input. In addition to the nodes provided at the input and output sections, each crossbar module is also provided with discrete input and output expansion portions through which the module may be linked to other identically configured crossbar modules when additional nodes are to be integrated into the system. The expansion ports allow serial linking of crossbar modules so as to establish a connection between source and destination nodes which are spread across different crossbar modules. The serially-linked expansion ports realize direct mapping between all system nodes in the form of a two-stage network; the basic crossbar design remains the same and there is no need for the problematic redesign of crossbar modules for accommodating added data transfer nodes. The modular crossbar design is particularly adapted for use with different system configurations having different numbers of communication nodes and permits a system to be upgraded by adding communication nodes by using additional identically configured crossbar modules.
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