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公开(公告)号：US08258013B1
公开(公告)日：2012-09-04
申请号：US12705441
申请日：2010-02-12
CPC分类号： H01L23/564 , H01L23/3128 , H01L23/3733 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/10253 , H01L2924/00
摘要： An integrated circuit package assembly includes a substrate, a semiconductor die having opposing first and second surfaces, and a head-spreader. The semiconductor die is mounted on the substrate with the first surface facing the substrate. The heat-spreader includes a central region thermally coupled to the second surface of the semiconductor die, a flange region mounted on the substrate, and a side wall region between the central and flange regions. A cavity is formed between the heat-spreader, the substrate, and the semiconductor die. The heat-spreader has at least one vent extending from the cavity through the heat-spreader.
摘要翻译： 集成电路封装组件包括衬底，具有相对的第一表面和第二表面的半导体管芯，以及头戴式撒布机。 半导体管芯安装在衬底上，第一表面面向衬底。 散热器包括热耦合到半导体管芯的第二表面的中心区域，安装在基板上的凸缘区域和中心区域和凸缘区域之间的侧壁区域。 在散热器，基板和半导体管芯之间形成空腔。 散热器具有至少一个从空腔延伸通过散热器的通风口。
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2.发明授权Structure and method of testing failed or returned die to determine failure location and type 失效测试的结构和方法失败或返回模具以确定故障位置和类型公开(公告)号：US06433360B1
公开(公告)日：2002-08-13
申请号：US09231733
申请日：1999-01-15
IPC分类号： H01L2358
CPC分类号： G01R1/0408 , G01R1/0483 , H01L2224/48091 , H01L2924/00014
摘要： A structure and method for testing a failed integrated circuit device includes a ball grid array substrate with its heat sink removed to form a cavity where a failed bare die is to be placed. An adhesive tape is attached to the lower surface of the ball grid array substrate covering the cavity, and the die is placed into the cavity against the sticky side of the adhesive tape. Wire bonds are formed from necessary pads on the die to electrical conductors on the substrate and the cavity and bond wires are covered with epoxy. When the epoxy is cured, the adhesive tape is removed, thus exposing the back side of the die for visual inspection while under test.
摘要翻译： 用于测试故障集成电路器件的结构和方法包括其栅极阵列衬底，其散热器被去除以形成其中将放置故障的裸露裸片的空腔。 将粘合带附着到覆盖空腔的球栅阵列基板的下表面，并将模具放置在抵靠胶带粘性侧的空腔中。 导线键由芯片上的必需焊盘形成在基板上的电导体上，并且空穴和接合线被环氧树脂覆盖。 当环氧树脂固化时，去除粘合带，从而在被测试时露出模具的背面以进行目视检查。
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3.发明授权Structure and method of testing failed or returned die to determine failure location and type 有权测试的结构和方法失败或返回模具以确定故障位置和类型公开(公告)号：US06768329B1
公开(公告)日：2004-07-27
申请号：US10174117
申请日：2002-06-17
IPC分类号： G01R3102
CPC分类号： G01R1/0408 , G01R1/0483 , H01L2224/48091 , H01L2924/00014
摘要： A structure and method for testing a failed integrated circuit device includes a ball grid array substrate with its heat sink removed to form a cavity where a failed bare die is to be placed. An adhesive tape is attached to the lower surface of the ball grid array substrate covering the cavity, and the die is placed into the cavity against the sticky side of the adhesive tape. Wire bonds are formed form necessary pads on the die to electrical conductors on the substrate and the cavity and bond wires are covered with epoxy. When the epoxy is cured, the adhesive tape is removed, thus exposing the back side of the die for visual inspection while under test.
摘要翻译： 用于测试故障集成电路器件的结构和方法包括其栅极阵列衬底，其散热器被去除以形成其中将放置故障的裸露裸片的空腔。 将粘合带附着到覆盖空腔的球栅阵列基板的下表面，并将模具放置在抵靠胶带粘性侧的空腔中。 线接头由芯片上必需的焊盘形成在基板上的电导体上，并且空穴和接合线被环氧树脂覆盖。 当环氧树脂固化时，去除粘合带，从而在被测试时露出模具的背面以进行目视检查。
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4.发明授权Integrated circuit package and method of forming an integrated circuit package 有权集成电路封装和形成集成电路封装的方法公开(公告)号：US08362609B1
公开(公告)日：2013-01-29
申请号：US12607019
申请日：2009-10-27
IPC分类号： H01L23/04
CPC分类号： H01L23/315 , H01L23/16 , H01L23/3128 , H01L23/4334 , H01L23/49816 , H01L23/642 , H01L2224/16225 , H01L2924/15311
摘要： An integrated circuit package is described. The integrated circuit package comprises a substrate having a plurality of sides, where each pair of adjacent sides forms a corner; a die coupled to a first surface of the substrate; a lid having a first portion positioned over the die and a plurality of foot portions, each foot portion of the plurality of foot portions being coupled to the first surface of the substrate at a corresponding corner of the substrate, where a side of the integrated circuit package above the substrate and between two associated foot portions has an opening; and a plurality of contact elements coupled to a second surface of the substrate. A method of forming an integrated circuit package is also shown.
摘要翻译： 描述了集成电路封装。 集成电路封装包括具有多个侧面的基板，其中每对相邻边形成拐角; 耦合到所述衬底的第一表面的裸片; 具有位于所述管芯上方的第一部分的盖和多个脚部，所述多个脚部的每个脚部在所述衬底的相应角部处联接到所述衬底的所述第一表面，其中所述集成电路的一侧 在衬底上方和两个相关联的脚部之间的封装具有开口; 以及耦合到所述衬底的第二表面的多个接触元件。 还示出了形成集成电路封装的方法。
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