公开(公告)号：US09628397B2

公开(公告)日：2017-04-18

申请号：US13447303

申请日：2012-04-16

Applicant: Kuo-Cheng Lu

Inventor： Kuo-Cheng Lu

IPC: H04L12/891 ,  H04L12/863

CPC classification number: H04L47/41 ,  H04L47/624

Abstract: The present invention discloses a communication device, including a first network interface, for receiving a plurality of packets composed of a plurality of first packets destined to a first communication device and a plurality of second packets, a first reordering engine, for reordering the plurality of first packets, outputting the plurality of reordered first packets, and outputting the plurality of second packets, a second reordering engine, for receiving the plurality of second packets from the first reordering engine, and reordering the plurality of second packets, a second network interface, for receiving the plurality of reordered first packets from the first reordering engine, and transmitting the plurality of reordered first packets to the first communication device, and a processing module, for processing the plurality of reordered second packets.

公开(公告)号：US08769322B2

公开(公告)日：2014-07-01

申请号：US13171461

申请日：2011-06-29

Applicant: Kuo-Cheng Lu

Inventor： Kuo-Cheng Lu

IPC: G06F1/00

CPC classification number: G06F1/08

Abstract: A method for adjusting clock frequency of a processing unit of a computer system includes calculating a busyness ratio of the processing unit according to a status signal provided by the processing unit, determining whether the busyness ratio is in a busyness ratio range, when the busyness ratio is not in the busyness ratio range, determining whether a calculation result generated according to a clock frequency of the processing unit and a frequency difference is in a frequency range, and when the calculation result is in the frequency range, adjusting the clock frequency of the processing unit according to the calculation result and outputting the adjusted clock frequency to a clock generator, wherein the busyness ratio range, the frequency range and the frequency difference are decided according to an operation state of a peripheral unit of the computer system.

Abstract translation: 一种用于调整计算机系统的处理单元的时钟频率的方法包括：根据由处理单元提供的状态信号计算处理单元的繁忙比，确定忙比是否在忙比范围，当忙比 不在忙比范围内，判断根据处理单元的时钟频率产生的计算结果和频率差是否在频率范围内，并且当计算结果在频率范围内时，调整时钟频率 处理单元，根据计算结果将调整后的时钟频率输出到时钟发生器，其中根据计算机系统的外围单元的操作状态来确定忙碌率范围，频率范围和频率差。

公开(公告)号：US20090318659A1

公开(公告)日：2009-12-24

申请号：US12484793

申请日：2009-06-15

Applicant: Ken-Yuan CHANG ,  Cheng-Tar Wu ,  Fa-Chen Chi ,  Kuo-Cheng Lu ,  Lin-Chien Yu

Inventor： Ken-Yuan CHANG ,  Cheng-Tar Wu ,  Fa-Chen Chi ,  Kuo-Cheng Lu ,  Lin-Chien Yu

IPC: C08G69/00

CPC classification number: C08G69/00 ,  C08G18/3829 ,  C08G18/4854 ,  C08G18/6681 ,  C08G18/831 ,  Y10T428/31504 ,  Y10T428/31507

Abstract: Disclosed herein is a biocidal polymer including at least one repeating unit of formula (A): wherein: R1 in each occurrence independently represents a divalent aromatic group containing 6 to 30 carbon atoms, a C2-C16 alkylene group or an alkylene biscyclohexyl; Y in each occurrence independently represents an oxygen atom or a sulfur atom; and Z1, Z2, Z3 and Z4 in each occurrence independently represent a hydrogen atom or a halogen atom; wherein at least one of Z1, Z2, Z3 and Z4 in the at least one repeating unit of formula (A) is a halogen atom. The preparation process and applications of the biocidal polymer are also disclosed.

Abstract translation: 本文公开了包含至少一种式（A）的重复单元的杀生物聚合物：其中：每次出现的R 1独立地表示含有6至30个碳原子的二价芳族基团，C 2 -C 16亚烷基或亚烷基双环己基; 每次出现的Y独立地表示氧原子或硫原子; 并且Z1，Z2，Z3和Z4各自独立地表示氢原子或卤素原子; 其中所述至少一个式（A）重复单元中的Z 1，Z 2，Z 3和Z 4中的至少一个为卤素原子。 还公开了杀生物聚合物的制备方法和应用。

公开(公告)号：US20090262739A1

公开(公告)日：2009-10-22

申请号：US12272761

申请日：2008-11-17

Applicant: Kuo-Cheng Lu

Inventor： Kuo-Cheng Lu

IPC: H04L12/56

CPC classification number: H04L49/9073 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9042

Abstract: A network device includes a first memory, a second memory, a receiver, a CPU, a transmitter, and a header cache controller (HCC). The HCC is coupled to the first memory and the second memory. The receiver, the CPU, and the transmitter access the first memory and the second memory via the HCC. The HCC can map an address of the first memory storing a header of a packet to an address of the second memory so as to store the header of the packet in the second memory.

Abstract translation: 网络设备包括第一存储器，第二存储器，接收器，CPU，发送器和头部高速缓存控制器（HCC）。 HCC耦合到第一存储器和第二存储器。 接收器，CPU和发射器通过HCC访问第一个存储器和第二个存储器。 HCC可以将存储分组报头的第一存储器的地址映射到第二存储器的地址，以便将数据包的报头存储在第二存储器中。

公开(公告)号：US09246846B2

公开(公告)日：2016-01-26

申请号：US13528844

申请日：2012-06-21

Applicant: Kuo-Yen Fan ,  Kuo-Cheng Lu

Inventor： Kuo-Yen Fan ,  Kuo-Cheng Lu

IPC: H04W4/00 ,  G06F15/16 ,  H04L12/933 ,  H04W88/16 ,  H04W92/02

CPC classification number: H04L49/15 ,  H04W88/16 ,  H04W92/02

Abstract: The present invention discloses a network processor for a broadband gateway. The network processor includes a host processor; a plurality of networking interfaces, corresponding to a plurality of networking technologies, respectively; and a network address translation (NAT) engine, for accelerating packet processing from a first networking interface to a second networking interface.

Abstract translation: 本发明公开了一种用于宽带网关的网络处理器。 网络处理器包括主机处理器; 分别对应于多个联网技术的多个网络接口; 以及网络地址转换（NAT）引擎，用于加速从第一网络接口到第二网络接口的分组处理。

公开(公告)号：US20130097349A1

公开(公告)日：2013-04-18

申请号：US13273232

申请日：2011-10-14

Applicant: Kuo-Cheng Lu ,  Chan-Shih Lin

Inventor： Kuo-Cheng Lu ,  Chan-Shih Lin

IPC: G06F13/37

CPC classification number: G06F13/161 ,  G06F13/36

Abstract: A quality of service (QoS) arbitration method for an on-chip bus is disclosed. The bus arbitration method includes steps of classifying each of a plurality of requestors into one of a plurality of first QoS types; classifying the each of the plurality of requestors into one of a plurality of second QoS types corresponding to a plurality of service priorities according to a due date or a data rate of the each of the plurality of requestors and the one of the plurality of first QoS types; and choosing a requestor with a highest service priority among the plurality of requestors to service.

Abstract translation: 公开了片上总线的服务质量（QoS）仲裁方法。 总线仲裁方法包括将多个请求者中的每一个分类为多个第一QoS类型之一的步骤; 根据多个请求者中的每一个的到期日期或数据速率和多个第一QoS中的一个，将多个请求者中的每一个分类为与多个服务优先级对应的多个第二QoS类型之一 类型 以及在所述多个请求者中选择具有最高服务优先级的请求者进行服务。

公开(公告)号：US07010705B2

公开(公告)日：2006-03-07

申请号：US10426796

申请日：2003-05-01

Applicant: Kuo-Cheng Lu

Inventor： Kuo-Cheng Lu

IPC: G06F1/32

CPC classification number: G06F1/3231 ,  G06F1/1626 ,  G06F1/1656 ,  G06F1/3203 ,  G06F1/3259 ,  G06F3/03543 ,  Y02D10/155 ,  Y02D10/173

Abstract: A method for triggering a power supply module switch of a cordless electric-apparatus which includes a metal inductive area and an electrostatic inductive element comprising the following steps: when a user body approaches the device to a predetermined distance which is less than the electrostatic induction distance, the electrostatic inductive element detects electrostatic charge from the user body so as to turn a switch within the electrostatic inductive element on; a power supply module supplies power for the cordless electric-apparatus when the switch is turned on; when the user body leaving away from the cordless electric-apparatus exceeds the electrostatic induction distance, the switch within the electrostatic inductive element turns off and when the switch turns off the power supply module supplies a part power for the cordless electric-apparatus.

Abstract translation: 一种用于触发包括金属感应区域和静电感应元件的无绳电气设备的电源模块开关的方法，包括以下步骤：当使用者身体接近小于静电感应距离的预定距离时 静电感应元件检测来自用户体的静电电荷，以使静电感应元件中的开关转动; 当开关打开时，电源模块为无绳电气设备供电; 当离开无绳电气设备的使用者身体超过静电感应距离时，静电感应元件内的开关断开，并且当开关断开时，电源模块为无绳电气设备供电。

公开(公告)号：US20130272311A1

公开(公告)日：2013-10-17

申请号：US13447303

申请日：2012-04-16

Applicant: Kuo-Cheng Lu

Inventor： Kuo-Cheng Lu

IPC: H04L12/56

CPC classification number: H04L47/41 ,  H04L47/624

Abstract: The present invention discloses a communication device, including a first network interface, for receiving a plurality of packets composed of a plurality of first packets destined to a first communication device and a plurality of second packets, a first reordering engine, for reordering the plurality of first packets, outputting the plurality of reordered first packets, and outputting the plurality of second packets, a second reordering engine, for receiving the plurality of second packets from the first reordering engine, and reordering the plurality of second packets, a second network interface, for receiving the plurality of reordered first packets from the first reordering engine, and transmitting the plurality of reordered first packets to the first communication device, and a processing module, for processing the plurality of reordered second packets.

Abstract translation: 本发明公开了一种包括第一网络接口的通信设备，用于接收由目的地为第一通信设备的多个第一分组和多个第二分组组成的多个分组，第一重新排序引擎，用于对多个 第一分组，输出所述多个重新排序的第一分组，以及输出所述多个第二分组;第二重新排序引擎，用于从所述第一重新排序引擎接收所述多个第二分组，以及重新排序所述多个第二分组，第二网络接口， 用于从第一重新排序引擎接收多个重新排序的第一分组，以及将多个重新排序的第一分组发送到第一通信设备，以及处理模块，用于处理多个重新排序的第二分组。

公开(公告)号：US20130058319A1

公开(公告)日：2013-03-07

申请号：US13528844

申请日：2012-06-21

Applicant: Kuo-Yen Fan ,  Kuo-Cheng Lu

Inventor： Kuo-Yen Fan ,  Kuo-Cheng Lu

IPC: H04L12/66 ,  H04W40/00 ,  H04W84/12 ,  H04L29/10

CPC classification number: H04L49/15 ,  H04W88/16 ,  H04W92/02

Abstract: The present invention discloses a network processor for a broadband gateway. The network processor includes a host processor; a plurality of networking interfaces, corresponding to a plurality of networking technologies, respectively; and a network address translation (NAT) engine, for accelerating packet processing from a first networking interface to a second networking interface.

Abstract translation: 本发明公开了一种用于宽带网关的网络处理器。 网络处理器包括主机处理器; 分别对应于多个联网技术的多个网络接口; 以及网络地址转换（NAT）引擎，用于加速从第一网络接口到第二网络接口的分组处理。

公开(公告)号：US07139267B2

公开(公告)日：2006-11-21

申请号：US10087761

申请日：2002-03-05

Applicant: Kuo-Cheng Lu ,  Hung-Kuang Chen

Inventor： Kuo-Cheng Lu ,  Hung-Kuang Chen

IPC: H04L12/50

CPC classification number: H04L45/02 ,  H04L45/58 ,  H04L49/201 ,  H04L49/351

Abstract: A network switch system that includes a plurality of first-level switches operating in a slave mode, the first-level switches providing a plurality of local ports for receiving and sending network packets, and a plurality of second-level switches operating in one of brain mode or master mode, wherein, the first-level switches includes a plurality of upward ports connecting to the second-level switches, each of the first-level switches and the second-level switches having a forwarding database, wherein the first-level switches sends the refresh packets to the second-level switches for synchronizing the forwarding databases of the second-level switches, wherein the second-level switches providing packet communications among the first-level switches, and wherein a second-level switch operating in the brain mode providing refresh packets to the first-level switches for synchronizing the forwarding databases of the first-level switches.