公开(公告)号：US06225160B1

公开(公告)日：2001-05-01

申请号：US09295067

申请日：1999-04-20

Applicant: Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

Inventor： Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/84

Abstract: A method of manufacturing a bottom electrode of a capacitor. A first dielectric layer is formed on a substrate. A cap layer is formed on the first dielectric layer. A second dielectric layer is formed on the cap layer. A node contact hole is formed to penetrate through the second dielectric layer, the cap layer and the first dielectric layer. A liner layer is formed on a sidewall of the node contact hole. A restraining layer is formed on the second dielectric layer. A patterned conductive layer is formed on a portion of the restraining layer and fills the node contact hole. A selective hemispherical grained layer is formed on the patterned conductive layer.

Abstract translation: 一种制造电容器的底部电极的方法。 在基板上形成第一电介质层。 在第一电介质层上形成覆盖层。 在盖层上形成第二电介质层。 形成节点接触孔以穿透第二介电层，盖层和第一介电层。 衬垫层形成在节点接触孔的侧壁上。 在第二电介质层上形成限制层。 在限制层的一部分上形成有图案的导电层，并填充节点接触孔。 在图案化的导电层上形成选择性半球形纹理层。

公开(公告)号：US06204107B1

公开(公告)日：2001-03-20

申请号：US09208611

申请日：1998-12-08

Applicant: Kuo-Chi Lin ,  Kuen-Yow Lin ,  Chien-Hua Tsai ,  Kun-Chi Lin

Inventor： Kuo-Chi Lin ,  Kuen-Yow Lin ,  Chien-Hua Tsai ,  Kun-Chi Lin

IPC: H01L218234

CPC classification number: H01L21/76831 ,  H01L21/76832

Abstract: A method for forming a multi-layered liner on the sidewalls of a node contact opening includes the steps of providing a substrate having a dielectric layer thereon. The dielectric layer further includes a node contact opening that exposes a portion of the substrate. A first liner layer is then formed on the sidewalls of the node contact opening. Next, a second liner layer is formed over the first liner layer such that the first liner layer and the second liner layer together form a dual-layered liner. The first liner layer in contact with the dielectric layer has good insulation capacity while the second liner layer has good etch-resisting property.

Abstract translation: 在节点接触开口的侧壁上形成多层衬垫的方法包括以下步骤：提供其上具有介电层的衬底。 电介质层还包括暴露基板的一部分的节点接触开口。 然后在节点接触开口的侧壁上形成第一衬垫层。 接下来，在第一衬里层上形成第二衬里层，使得第一衬里层和第二衬里层一起形成双层衬垫。 与电介质层接触的第一衬垫层具有良好的绝缘能力，而第二衬垫层具有良好的抗蚀性能。

公开(公告)号：US6150216A

公开(公告)日：2000-11-21

申请号：US222737

申请日：1998-12-29

Applicant: Kuo-Chi Lin ,  Kun-Chi Lin

Inventor： Kuo-Chi Lin ,  Kun-Chi Lin

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/20 ,  H01G4/06 ,  H01G4/30

CPC classification number: H01L28/84 ,  H01L21/76895 ,  H01L27/10855 ,  H01L28/60

Abstract: A method for forming an electrode of semiconductor device capacitor is disclosed. The method comprises forming a dielectric layer on a semiconductor substrate and then using photolithographic method to etch a trench through the dielectric layer to expose specific part of the semiconductor substrate. A polysilicon layer is then formed over the dielectric layer and filled the trench. The polysilicon layer is patterned by a photoresist layer and etched back to the dielectric layer, then a polysilicon rod is formed. A spacer method is used to form an amorphized silicon spacer is sidewall of the polysilicon rod. The polysilicon rod is then implanted to form an amorphized polysilicon layer on top surface of the polysilicon rod. Final hemispherical grain silicon is formed on the spacer and the amorphized polysilicon layer to increase the surface area of the polysilicon rod. Thereby, an electrode of a semiconductor device capacitor is formed, and the capacitance of capacitor is enhanced.

Abstract translation: 公开了一种形成半导体器件电容器的电极的方法。 该方法包括在半导体衬底上形成电介质层，然后使用光刻法蚀刻通过电介质层的沟槽，以露出半导体衬底的特定部分。 然后在电介质层上形成多晶硅层，并填充沟槽。 通过光致抗蚀剂层将多晶硅层图案化并回蚀刻到电介质层，然后形成多晶硅棒。 使用间隔法形成非晶硅衬垫是多晶硅棒的侧壁。 然后植入多晶硅棒以在多晶硅棒的顶表面上形成非晶化多晶硅层。 在间隔物和非晶化多晶硅层上形成最终的半球形晶粒硅以增加多晶硅棒的表面积。 由此，形成半导体器件电容器的电极，提高电容器的电容。

公开(公告)号：US06191042B1

公开(公告)日：2001-02-20

申请号：US09246761

申请日：1999-02-08

Applicant: Chien-Hua Tsai ,  Kuo-Chi Lin

Inventor： Chien-Hua Tsai ,  Kuo-Chi Lin

IPC: H01L21311

CPC classification number: H01L21/31116 ,  H01L21/76804 ,  H01L21/76816

Abstract: A method of fabricating a node contact opening includes formation of a dielectric layer on a substrate. An opening is formed with C4F8/Ar/CH2F2 as an etchant. A portion of the dielectric layer under the opening is etched with CHF3/CO as an etchant until the substrate is exposed. A node contact opening is formed.

Abstract translation: 制造节点接触开口的方法包括在基底上形成电介质层。 用C4F8 / Ar / CH2F2作为蚀刻剂形成开口。 用CHF 3 / CO作为蚀刻剂蚀刻开口下方的电介质层的一部分，直到基板露出。 形成节点接触开口。

公开(公告)号：US6150215A

公开(公告)日：2000-11-21

申请号：US371415

申请日：1999-08-10

Applicant: Kuo-Chi Lin ,  Da-Wen Hsia

Inventor： Kuo-Chi Lin ,  Da-Wen Hsia

IPC: H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/10852

Abstract: A method for ensuring no capacitor peeling at the edge of a wafer in the fabrication of dynamic random access memory (DRAM) is disclosed. The method includes first providing a semiconductor substrate having a semiconductor structure formed thereon. A dielectric layer is then formed overlying the semiconductor structure, and patterned for defining a contact window. Followed by, the deposition of a silicon layer over the dielectric layer that fills up the contact window. Consequentially, a photoresist layer is coated overlying the silicon layer, where it will be rinsed twice by a combination of an online EBR (and/or a WEE) and an offline EBR at a distance inwardly away from the edge of the wafer in process for removing a portion of the photoresist to avoid abnormal capacitor formation in later stages. Then, a photolithography process is carried out against the photoresist layer to form a photoresist mask. Finally, the silicon layer is etched where it is not covered by the photoresist mask to form a lower capacitor electrode. The photoresist mask is stripped as to conclude the present invention.

Abstract translation: 公开了一种在制造动态随机存取存储器（DRAM）中确保在晶片边缘没有电容器剥离的方法。 该方法包括首先提供其上形成有半导体结构的半导体衬底。 然后形成覆盖半导体结构的电介质层，并且被图案化以限定接触窗口。 随后，在填充接触窗口的电介质层上沉积硅层。 因此，将光致抗蚀剂层涂覆在硅层上，其中将通过在线EBR（和/或WEE）和离线EBR的组合在离晶片边缘的距离内漂洗两次，所述离线EBR在工艺中为 去除一部分光致抗蚀剂以避免后期阶段电容器形成异常。 然后，对光致抗蚀剂层进行光刻工艺以形成光致抗蚀剂掩模。 最后，硅层被蚀刻，其未被光致抗蚀剂掩模覆盖，以形成较低的电容器电极。 剥离光致抗蚀剂掩模以得出本发明。

公开(公告)号：US6074912A

公开(公告)日：2000-06-13

申请号：US245891

申请日：1999-02-08

Applicant: Kuen-Yow Lin ,  Kuo-Chi Lin

Inventor： Kuen-Yow Lin ,  Kuo-Chi Lin

IPC: H01L21/60 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L27/10873

Abstract: A method for forming different area vias of dynamic random access memory is disclosed. Essential points of the invention comprise spacer is only formed on gate of periphery circuit, and depth of passivation layer of periphery circuit gates is larger than depth of layer that capped over gates of cell. The provided method comprises following steps: First, capping a layer over gate of cell and gate of periphery circuit and then forming spacer on gate of periphery circuit, where depth of capping layer is smaller than depth of passivation layer of periphery circuit gate. Second, both gate of cell and gate of periphery circuit are cover by a dielectric layer. Third, vias in both cell and periphery circuit are formed simultaneously by photolithography and etching, where etching comprises etching of dielectric layer and etching of passivation layer. Advantageous of the invention is only a photolithography process is necessary and then throughput is enhanced.

Abstract translation: 公开了形成动态随机存取存储器的不同区域通孔的方法。 本发明的要点包括仅在外围电路的栅极上形成间隔物，并且外围电路栅极的钝化层的深度大于封闭电池栅极的层的深度。 提供的方法包括以下步骤：首先，在外围电路的单元和栅极的栅极上覆盖一层，然后在外围电路的栅极上形成间隔，其中覆盖层的深度小于外围电路栅极的钝化层的深度。 第二，外围电路的栅极和栅极的栅极被介电层覆盖。 第三，通过光刻和蚀刻同时形成电池和外围电路中的通孔，其中蚀刻包括蚀刻介电层和蚀刻钝化层。 本发明的有益之处在于仅需要光刻工艺，并且提高生产量。

公开(公告)号：US08541973B2

公开(公告)日：2013-09-24

申请号：US12623433

申请日：2009-11-22

Applicant: Sheng-Yu Tseng ,  Ying-Jhih Wu ,  Kuo-Chi Lin

Inventor： Sheng-Yu Tseng ,  Ying-Jhih Wu ,  Kuo-Chi Lin

IPC: H01M10/46

CPC classification number: H02J7/0065 ,  H02J7/355 ,  H02M3/1582

Abstract: A single stage low boost/buck ratio stand-alone solar energy power generating circuit with a system thereof is a simplification of a two-stage type circuit. The two-stage circuit, which has a storage unit, a charging converter circuit for charging the storage unit, and a discharging converter circuit for discharging the stored power to a load, is analyzed and categorized such that a circuit structure is selected via a suitable simplified combination to commonly use the elements constituting the charging and the discharging converter circuits so as to form the single stage circuit with less elements, volume and weight for reducing the production cost of the circuit.

Abstract translation: 具有其系统的单级低升压/降压比独立太阳能发电电路是两级型电路的简化。 具有存储单元的两级电路，用于对存储单元充电的充电转换器电路和用于将存储的电力放电到负载的放电转换器电路进行分析和分类，使得经由适当的 通常使用构成充电和放电转换器电路的元件的简化组合，以便形成具有较少元件，体积和重量的单级电路，以降低电路的生产成本。

公开(公告)号：US08371776B2

公开(公告)日：2013-02-12

申请号：US12620568

申请日：2009-11-17

Applicant: Kuo-Chi Lin

Inventor： Kuo-Chi Lin

IPC: B23B29/02

CPC classification number: B23B27/002 ,  B23B27/007 ,  B23B2250/16 ,  B23B2260/138 ,  Y10T82/2585 ,  Y10T408/76

Abstract: A cutting tool includes a blade, a seat, a shank and a damper. The blade is connected to the seat. The seat is connected to the shank. The shank includes a pocket defined therein and a thread formed on the wall of the pocket. A damper is inserted in the pocket. The damper includes a thread formed on the periphery for engagement with the thread of the shank, with a small gap defined between the threads.

Abstract translation: 切割工具包括刀片，座椅，柄和阻尼器。 刀片连接到座椅。 座椅连接到柄。 柄包括限定在其中的口袋和形成在口袋的壁上的线。 在口袋中插入阻尼器。 阻尼器包括形成在周边上用于与柄的螺纹接合的螺纹，在螺纹之间限定有小的间隙。

公开(公告)号：US08292134B2

公开(公告)日：2012-10-23

申请号：US12959428

申请日：2010-12-03

Applicant: Kuo-Chi Lin

Inventor： Kuo-Chi Lin

IPC: A41D27/22

CPC classification number: A47G25/186 ,  A47G25/30 ,  A47G25/40

Abstract: A multifunction clothes hanger includes a main body, a hook, an annular member and two clothes hangers. A protrusion of a cylindrical body of each clothes hanger enters a T-shaped through-groove at the bottom of the main body and moves into a transverse portion of the T-shaped through-groove to enter left and right through-holes of the main body. The protrusion is engaged with grooves disposed on the inner sides of the left and right through-holes, respectively. Furthermore, the hook is inserted into a straight through-hole at the upper portion of the main body until the threaded bottom with a thread thereon reaches the bottom of the main body to engage with a screw nut of the annular member. Another space-saving multifunction clothes hanger further includes a fixing base, upper and lower arms, two grooves, left and right baffles and two screw holes.

Abstract translation: 多功能衣架包括主体，钩，环形构件和两个衣架。 每个衣架的圆柱体的突出部进入主体底部的T形通槽，并移动到T形通槽的横向部分中，以进入主体的左右通孔 身体。 突起与分别设置在左右通孔的内侧的槽接合。 此外，将钩子插入到主体上部的直通孔中，直到其上有螺纹的螺纹底部到达主体的底部以与环形构件的螺母接合。 另一个节省空间的多功能衣架还包括固定底座，上下臂，两个凹槽，左右挡板和两个螺孔。

公开(公告)号：US20100322722A1

公开(公告)日：2010-12-23

申请号：US12865552

申请日：2008-06-13

Applicant: Kuo-Chi Lin

Inventor： Kuo-Chi Lin

IPC: B23B27/10 ,  B23B29/12

CPC classification number: B23B27/007 ,  B23B29/046 ,  B23B31/1075 ,  B23B2250/12 ,  Y10T407/14 ,  Y10T407/227

Abstract: A combinative cutter includes a holder, a shank, a blade and at least two screws. The holder includes an eccentric bore defined at an end and at least two screw holes in communication with the eccentric bore. The shank is inserted in the eccentric bore and formed with a planar face. The blade is attached to an end of the shank extending beyond the holder. The screws are driven through the screw holes and abutted against the planar face to keep the shank in the eccentric bore.

Abstract translation: 组合切割器包括保持器，柄，刀片和至少两个螺钉。 保持器包括限定在端部的偏心孔和与偏心孔连通的至少两个螺纹孔。 柄部插入偏心孔中并形成平面。 刀片附接到延伸超过保持器的柄的一端。 螺钉被驱动穿过螺钉孔并抵靠在平面上以将柄保持在偏心孔中。