公开(公告)号：US08664701B2

公开(公告)日：2014-03-04

申请号：US13446327

申请日：2012-04-13

申请人： Kuo-Liang Chao ,  Mei-Ling Chen ,  Hung-Hsin Kuo

发明人： Kuo-Liang Chao ,  Mei-Ling Chen ,  Hung-Hsin Kuo

IPC分类号： H01L21/02 ,  H01L21/322

CPC分类号： H01L29/66143 ,  H01L21/28017 ,  H01L21/3086 ,  H01L29/407 ,  H01L29/456 ,  H01L29/66136 ,  H01L29/7813 ,  H01L29/861

摘要： A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure.

摘要翻译： 提供一种制造具有垂直MOS结构的整流器的方法。 第一沟槽结构和第一掩模层形成在半导体衬底的第一侧。 第二沟槽结构形成在半导体衬底的第二侧。 栅极氧化层，多晶硅结构和金属溅射层依次形成在第二沟槽结构上。 整流器还包括湿式氧化物层和多个掺杂区域。 在第一多沟槽结构的表面和半导体衬底中形成湿氧化物层。 掺杂区形成在半导体衬底和第二沟槽结构之间的区域上，并且位于掩模层旁边。 金属溅射层形成在对应于第一沟槽结构的第一掩模层上。

公开(公告)号：US08680590B2

公开(公告)日：2014-03-25

申请号：US13411035

申请日：2012-03-02

申请人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

发明人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

IPC分类号： H01L21/02 ,  H01L21/44

CPC分类号： H01L21/28008 ,  H01L29/0619 ,  H01L29/4236 ,  H01L29/66143 ,  H01L29/66621 ,  H01L29/8725

摘要： A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.

摘要翻译： 公开了半导体器件的多沟槽端接结构，其中半导体器件包括半导体衬底和有源结构区域。 所述多沟槽端接结构包括限定在所述半导体衬底的暴露表面上的多个沟槽，形成在所述半导体衬底的部分暴露表面上并对应于所述半导体器件的端接结构区域的第一掩模层，形成的栅极绝缘层 在所述沟槽中，形成在所述栅绝缘层上并从所述半导体衬底的暴露表面突出的导电层，以及形成在所述半导体器件的所述端接结构区域上的所述第一掩模层和导电层上的金属层。

公开(公告)号：US20130228891A1

公开(公告)日：2013-09-05

申请号：US13411035

申请日：2012-03-02

申请人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

发明人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/28008 ,  H01L29/0619 ,  H01L29/4236 ,  H01L29/66143 ,  H01L29/66621 ,  H01L29/8725

摘要： A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.

摘要翻译： 公开了半导体器件的多沟槽端接结构，其中半导体器件包括半导体衬底和有源结构区域。 所述多沟槽端接结构包括限定在所述半导体衬底的暴露表面上的多个沟槽，形成在所述半导体衬底的部分暴露表面上并对应于所述半导体器件的端接结构区域的第一掩模层，形成的栅极绝缘层 在所述沟槽中，形成在所述栅绝缘层上并从所述半导体衬底的暴露表面突出的导电层，以及形成在所述半导体器件的所述端接结构区域上的所述第一掩模层和导电层上的金属层。

公开(公告)号：US08796808B2

公开(公告)日：2014-08-05

申请号：US12427256

申请日：2009-04-21

申请人： Kuo-Liang Chao ,  Hung-Hsin Kuo ,  Tse-Chuan Su

发明人： Kuo-Liang Chao ,  Hung-Hsin Kuo ,  Tse-Chuan Su

IPC分类号： H01L29/47

CPC分类号： H01L29/66848 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/66143 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/872

摘要： A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.

摘要翻译： MOS PN结肖特基二极管器件包括具有第一导电类型的衬底，限定沟槽结构的场氧化物结构，形成在沟槽结构中的栅极结构以及与衬底中的栅极结构相邻的具有第二导电类型的掺杂区 。 在栅极结构的不同侧形成欧姆接触和肖特基接触。 制造这种二极管器件的方法包括几个离子注入步骤，以形成具有不同注入深度的多个掺杂子区域以构成掺杂区域。 形成的MOS P-N结肖特基二极管器件具有低正向压降，低反向漏电流，快速反向恢复时间和高反向电压容限。

公开(公告)号：US08390081B2

公开(公告)日：2013-03-05

申请号：US12427223

申请日：2009-04-21

申请人： Kuo-Liang Chao ,  Hung-Hsin Kuo ,  Tse-Chuan Su

发明人： Kuo-Liang Chao ,  Hung-Hsin Kuo ,  Tse-Chuan Su

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/66356 ,  H01L29/7391

摘要： A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.

摘要翻译： MOS P-N结二极管器件包括具有第一导电类型的衬底，限定沟槽结构的场氧化物结构，形成在沟槽结构中的栅极结构以及与衬底中的栅极结构相邻的具有第二导电类型的掺杂区。 用于制造这种二极管器件的方法包括几个离子注入步骤。 在通过使用图案化光致抗蚀剂层作为掩模的各向同性蚀刻形成栅极结构之后，使用图案化的光致抗蚀剂层作为掩模进行离子注入步骤，以形成更深的掺杂子区域。 然后，使用栅极结构作为掩模来执行另一个离子注入步骤，以在栅极结构和较深掺杂的子区域之间形成较浅的掺杂子区域。 形成的MOS P-N结二极管器件具有低正向压降，低反向漏电流，快速反向恢复时间和高反向电压容限。