公开(公告)号：US08680590B2

公开(公告)日：2014-03-25

申请号：US13411035

申请日：2012-03-02

申请人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

发明人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

IPC分类号： H01L21/02 ,  H01L21/44

CPC分类号： H01L21/28008 ,  H01L29/0619 ,  H01L29/4236 ,  H01L29/66143 ,  H01L29/66621 ,  H01L29/8725

摘要： A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.

摘要翻译： 公开了半导体器件的多沟槽端接结构，其中半导体器件包括半导体衬底和有源结构区域。 所述多沟槽端接结构包括限定在所述半导体衬底的暴露表面上的多个沟槽，形成在所述半导体衬底的部分暴露表面上并对应于所述半导体器件的端接结构区域的第一掩模层，形成的栅极绝缘层 在所述沟槽中，形成在所述栅绝缘层上并从所述半导体衬底的暴露表面突出的导电层，以及形成在所述半导体器件的所述端接结构区域上的所述第一掩模层和导电层上的金属层。

公开(公告)号：US20130228891A1

公开(公告)日：2013-09-05

申请号：US13411035

申请日：2012-03-02

申请人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

发明人： Lung-Ching Kao ,  Mei-Ling Chen ,  Kuo-Liang Chao ,  Hung-Hsin Kuo

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/28008 ,  H01L29/0619 ,  H01L29/4236 ,  H01L29/66143 ,  H01L29/66621 ,  H01L29/8725

摘要： A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.

摘要翻译： 公开了半导体器件的多沟槽端接结构，其中半导体器件包括半导体衬底和有源结构区域。 所述多沟槽端接结构包括限定在所述半导体衬底的暴露表面上的多个沟槽，形成在所述半导体衬底的部分暴露表面上并对应于所述半导体器件的端接结构区域的第一掩模层，形成的栅极绝缘层 在所述沟槽中，形成在所述栅绝缘层上并从所述半导体衬底的暴露表面突出的导电层，以及形成在所述半导体器件的所述端接结构区域上的所述第一掩模层和导电层上的金属层。

公开(公告)号：US20120223421A1

公开(公告)日：2012-09-06

申请号：US13406071

申请日：2012-02-27

申请人： Hung-Ping Tsai ,  Shih-Kuan Chen ,  Lung-Ching Kao

发明人： Hung-Ping Tsai ,  Shih-Kuan Chen ,  Lung-Ching Kao

IPC分类号： H01L29/861

CPC分类号： H01L29/6609 ,  H01L29/0657 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/868

摘要： A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.

摘要翻译： 高功率密度或低正向电压整流器，其利用阳极和阴极中的至少一个沟槽。 沟槽形成在基板的相对表面中，以增加半导体管芯的每单位表面积的结表面积。 这种结构允许增加电流负载而不增加水平管芯空间。 增加的电流处理能力允许整流器以较低的正向电压工作。 此外，本发明的结构提供了高达30％的基板使用量。

公开(公告)号：US20120199902A1

公开(公告)日：2012-08-09

申请号：US13021078

申请日：2011-02-04

申请人： Lung-Ching Kao

发明人： Lung-Ching Kao

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/8725 ,  H01L29/407

摘要： A semiconductor rectifier is provided which includes a semiconductor substrate having a first type of conductivity. An epitaxial layer is formed on the substrate. The epitaxial layer has the first type of conductivity and is more lightly doped than the substrate. A plurality of floating gates is formed in the epitaxial layer and a metal layer is disposed over the epitaxial layer to form a Schottky contact therebetween. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

摘要翻译： 提供一种半导体整流器，其包括具有第一类导电性的半导体衬底。 在基板上形成外延层。 外延层具有第一类导电性，并且比衬底更轻掺杂。 在外延层中形成多个浮置栅极，并且在外延层上设置金属层以在它们之间形成肖特基接触。 第一电极形成在金属层的上方，第二电极形成在基板的背面。

公开(公告)号：US20110084332A1

公开(公告)日：2011-04-14

申请号：US12575517

申请日：2009-10-08

申请人： Lung-Ching Kao

发明人： Lung-Ching Kao

IPC分类号： H01L29/78 ,  H01L21/302 ,  H01L21/28

CPC分类号： H01L29/7811 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8725

摘要： A trench MOS device includes a base semiconductor substrate, an epitaxial layer grown on the base semiconductor substrate, a first trench in the epitaxial layer, and a stepped trench comprising a second trench and a third trench in the epitaxial layer. There is a mesa between the first trench and the stepped trench. There is a spacer on a the sidewall of the second trench, wherein the third trench having a depth below the spacer. There is a dielectric layer extending along sidewalls and bottom walls of the second trench and the third trench. There is also a metal layer extending over the first trench, over a sidewall of the stepped trench and a portion of the bottom of the stepped trench.

摘要翻译： 沟槽MOS器件包括基底半导体衬底，在基底半导体衬底上生长的外延层，外延层中的第一沟槽和在外延层中包括第二沟槽和第三沟槽的阶梯形沟槽。 在第一沟槽和阶梯式沟槽之间存在台面。 在第二沟槽的侧壁上有间隔件，其中第三沟槽的深度位于间隔件的下方。 存在沿着第二沟槽和第三沟槽的侧壁和底壁延伸的介电层。 还有在第一沟槽上方延伸的金属层，在阶梯状沟槽的侧壁和阶梯状沟槽的底部的一部分之上。

公开(公告)号：US20080079020A1

公开(公告)日：2008-04-03

申请号：US11542420

申请日：2006-10-03

申请人： Lung-Ching Kao ,  Pu-Ju Kung

发明人： Lung-Ching Kao ,  Pu-Ju Kung

IPC分类号： H01L29/74

CPC分类号： H01L29/87 ,  H01L29/0661

摘要： A multiple layer overvoltage protection device is provided. The method begins by providing a substrate having a first impurity concentration of a first conductivity type to define a mid-region layer. A dopant of a second conductivity type is introduced into the substrate with a second impurity concentration less than the first impurity concentration. An upper base region having a second type of conductivity is formed on the upper surface of the mid-region layer. A lower base region layer having a second type of conductivity is formed on a lower surface of the mid-region layer. A first emitter region having a first type of conductivity is formed on a surface of the upper base region layer. A first metal contact is coupled to the upper base region layer and a second metal contact is coupled to the lower base region layer.

摘要翻译： 提供多层过电压保护装置。 该方法开始于提供具有第一导电类型的第一杂质浓度的衬底以限定中间区域层。 将第二导电类型的掺杂剂引入到具有小于第一杂质浓度的第二杂质浓度的衬底中。 在中区域层的上表面上形成具有第二导电类型的上基区。 在中区域层的下表面上形成具有第二导电类型的下基底区域。 具有第一类型的导电性的第一发射极区域形成在上部基极区域的表面上。 第一金属触点耦合到上基极区域层，第二金属触点耦合到下基极区域层。

公开(公告)号：US08125056B2

公开(公告)日：2012-02-28

申请号：US12565201

申请日：2009-09-23

申请人： Hung-Ping Tsai ,  Shih-Kuan Chen ,  Lung-Ching Kao

发明人： Hung-Ping Tsai ,  Shih-Kuan Chen ,  Lung-Ching Kao

IPC分类号： H01L29/06

CPC分类号： H01L29/6609 ,  H01L29/0657 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/868

摘要： A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.

摘要翻译： 高功率密度或低正向电压整流器，其利用阳极和阴极中的至少一个沟槽。 沟槽形成在基板的相对表面中，以增加半导体管芯的每单位表面积的结表面积。 这种结构允许增加电流负载而不增加水平管芯空间。 增加的电流处理能力允许整流器在较低的正向电压下工作。 此外，本发明的结构提供了高达30％的基板使用量。

公开(公告)号：US08643152B2

公开(公告)日：2014-02-04

申请号：US13406071

申请日：2012-02-27

申请人： Hung-Ping Tsai ,  Shih-Kuan Chen ,  Lung-Ching Kao

发明人： Hung-Ping Tsai ,  Shih-Kuan Chen ,  Lung-Ching Kao

IPC分类号： H01L29/06

CPC分类号： H01L29/6609 ,  H01L29/0657 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/868

摘要： A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.

摘要翻译： 高功率密度或低正向电压整流器，其利用阳极和阴极中的至少一个沟槽。 沟槽形成在基板的相对表面中，以增加半导体管芯的每单位表面积的结表面积。 这种结构允许增加电流负载而不增加水平管芯空间。 增加的电流处理能力允许整流器以较低的正向电压工作。 此外，本发明的结构提供了高达30％的基板使用量。

公开(公告)号：US08461646B2

公开(公告)日：2013-06-11

申请号：US13021078

申请日：2011-02-04

申请人： Lung-Ching Kao

发明人： Lung-Ching Kao

IPC分类号： H01L29/88 ,  H01L21/28

CPC分类号： H01L29/8725 ,  H01L29/407

摘要： A semiconductor rectifier is provided which includes a semiconductor substrate having a first type of conductivity. An epitaxial layer is formed on the substrate. The epitaxial layer has the first type of conductivity and is more lightly doped than the substrate. A plurality of floating gates is formed in the epitaxial layer and a metal layer is disposed over the epitaxial layer to form a Schottky contact therebetween. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

摘要翻译： 提供一种半导体整流器，其包括具有第一类导电性的半导体衬底。 在基板上形成外延层。 外延层具有第一类导电性，并且比衬底更轻掺杂。 在外延层中形成多个浮置栅极，并且在外延层上设置金属层以在它们之间形成肖特基接触。 第一电极形成在金属层的上方，第二电极形成在基板的背面。

公开(公告)号：US20120200975A1

公开(公告)日：2012-08-09

申请号：US13366944

申请日：2012-02-06

申请人： Lung-Ching Kao ,  Pu-Ju Kung ,  Yu-Ju Yu

发明人： Lung-Ching Kao ,  Pu-Ju Kung ,  Yu-Ju Yu

IPC分类号： H02H3/22 ,  H01R43/00

CPC分类号： H01L29/868 ,  H01L27/0814 ,  H01L27/0817 ,  H01L29/861 ,  H01L29/872 ,  Y10T29/49117 ,  Y10T29/49169 ,  Y10T29/49171

摘要： A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.

摘要翻译： 低正向压降瞬态电压抑制器利用在单个集成电路器件中与高反向电压额定肖特基整流器并联电连接的低反向电压额定PN二极管。 瞬态电压抑制器非常适合固定PN二极管的高正向压降和肖特基整流器低反向击穿的高泄漏问题。 低反向电压PN整流器可以通过以下方法制造：1）双层epi（底部具有较高浓度层epi）或2）通过压缩的基极通过PN二极管的穿孔设计。