公开(公告)号：US11646309B2

公开(公告)日：2023-05-09

申请号：US17827705

申请日：2022-05-28

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist

IPC分类号： H01L27/06 ,  G03F9/00 ,  H01L21/762 ,  H01L21/84 ,  H01L23/48 ,  H01L23/544 ,  H01L27/02 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/812 ,  H01L29/423 ,  H01L29/732 ,  H01L29/808 ,  H01L21/768 ,  H01L21/822 ,  H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L21/268 ,  H01L27/088

CPC分类号： H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20 ,  H01L21/268 ,  H01L24/73 ,  H01L27/088 ,  H01L29/66545 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025

摘要： A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; a via disposed through the second level, where each of the second transistors includes a metal gate, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

公开(公告)号：US20170207183A1

公开(公告)日：2017-07-20

申请号：US15249696

申请日：2016-08-29

申请人： Mitsubishi Electric Corporation

发明人： Naoto ANDO

IPC分类号： H01L23/00 ,  H01L29/40 ,  H01L23/66 ,  H01L21/56 ,  H01L23/31 ,  H01L29/66 ,  H01L21/48 ,  H01L29/812 ,  H01L23/495

CPC分类号： H01L23/564 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/66 ,  H01L24/48 ,  H01L29/408 ,  H01L29/66848 ,  H01L29/66863 ,  H01L29/8128 ,  H01L2223/6683 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/1423 ,  H01L2224/45099

摘要： A semiconductor device includes: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a gate electrode on the semiconductor layer between the source electrode and the drain electrode; and an insulating film covering the semiconductor layer, the source electrode, the drain electrode and the gate electrode, the gate electrode has an eaves structure including a lower electrode joined to the semiconductor layer and an upper electrode provided on the lower electrode and wider than the lower electrode, a principal ingredient of the insulating film is an oxide film where atomic layers are alternately arrayed for each monolayer, and a film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to a film thickness of the insulating film that covers the upper electrode.

公开(公告)号：US20170133518A1

公开(公告)日：2017-05-11

申请号：US15405827

申请日：2017-01-13

申请人： United Silicon Carbide, Inc.

发明人： Zhongda Li ,  Anup Bhalla

IPC分类号： H01L29/812 ,  H01L29/66 ,  H01L29/47 ,  H01L29/06

CPC分类号： H01L29/8122 ,  H01L21/045 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/047 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/76897 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66007 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/665 ,  H01L29/66848 ,  H01L29/66856 ,  H01L29/66909 ,  H01L29/66969 ,  H01L29/8083 ,  H01L29/8128

摘要： A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

公开(公告)号：US09419083B2

公开(公告)日：2016-08-16

申请号：US14550557

申请日：2014-11-21

申请人： Raytheon Company

发明人： John P. Bettencourt ,  Eduardo M. Chumbes

IPC分类号： H01L21/338 ,  H01L29/40 ,  H01L29/812 ,  H01L29/66 ,  H01L21/28

CPC分类号： H01L29/402 ,  H01L21/28026 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/66848 ,  H01L29/778 ,  H01L29/812

摘要： A field effect transistor structure having a semiconductor having a source region, a drain region, and a gate contact region disposed between the source region and the drain region; and a gate electrode having a stem section extending from a top section of the gate electrode to, and in Schottky contact with, the gate contact region. The stem section has an upper portion terminating at the top portion of the gate electrode and a bottom portion narrower than the upper portion, the bottom portion terminating at the gate contact region. The bottom portion of the stem has a step between the upper portion of the stem section and the bottom portion of the stem section in only one side of the stem section. The step of the stem section provides an asymmetric field plate for the field effect transistor.

摘要翻译： 一种场效应晶体管结构，其具有设置在源极区域和漏极区域之间的源区域，漏极区域和栅极接触区域的半导体; 以及栅电极，其具有从栅电极的顶部延伸到与栅极接触区域肖特基接触的杆部分。 杆部分具有终止于栅电极的顶部的上部部分和比上部部分窄的底部部分，底部部分终止于栅极接触区域。 杆的底部在杆部的仅一侧具有杆段的上部和杆部的底部之间的台阶。 杆段的步骤为场效应晶体管提供了不对称的场板。

公开(公告)号：US20160211140A1

公开(公告)日：2016-07-21

申请号：US14997221

申请日：2016-01-15

申请人： Infineon Technologies AG

发明人： Jens Peter Konrath ,  Ronny Kern ,  Stefan Krivec ,  Ulrich Schmid ,  Laura Stoeber

IPC分类号： H01L21/285 ,  H01L21/265 ,  H01L29/47

CPC分类号： H01L21/28537 ,  H01L21/02046 ,  H01L21/02049 ,  H01L21/0455 ,  H01L21/0495 ,  H01L21/2236 ,  H01L21/2652 ,  H01L21/67115 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/36 ,  H01L29/365 ,  H01L29/401 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/66848 ,  H01L29/872

摘要： A method for processing a semiconductor includes irradiating a surface of a semiconductor with ions of a first gas type for cleaning the surface and implanting of ions of a second gas type in a region below the surface of the semiconductor for creating defects in the region below the surface. The irradiating and the implanting are performed within the same chamber.

摘要翻译： 一种用于处理半导体的方法包括用半导体的表面照射用于清洁表面的第一气体类型的离子和将第二气体类型的离子注入到半导体表面下方的区域中，用于在低于该半导体区域的区域内产生缺陷 表面。 照射和植入在相同的室内进行。

公开(公告)号：US20160204113A1

公开(公告)日：2016-07-14

申请号：US14994516

申请日：2016-01-13

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Gong ZHANG

IPC分类号： H01L27/11

CPC分类号： H01L27/1104 ,  H01L29/0891 ,  H01L29/66848 ,  H01L29/78624 ,  H01L29/812

摘要： A semiconductor device may include a first inverter, a second inverter, a first access transistor, and a second access transistor. A drain electrode of the first access transistor or a source electrode of the first access transistor may be electrically connected to both an output terminal of the first inverter and an input terminal the second inverter. The drain electrode of the first access transistor may be asymmetrical to the source electrode of the first access transistor with reference to a gate electrode of the first access transistor. A drain electrode of the second access transistor or a source electrode of the second access transistor may be electrically connected to both an output terminal of the second inverter and an input terminal the first inverter.

摘要翻译： 半导体器件可以包括第一反相器，第二反相器，第一存取晶体管和第二存取晶体管。 第一存取晶体管的漏电极或第一存取晶体管的源电极可以电连接到第一反相器的输出端和第二反相器的输入端。 参考第一存取晶体管的栅电极，第一存取晶体管的漏电极可能与第一存取晶体管的源电极不对称。 第二存取晶体管的漏电极或第二存取晶体管的源极可以电连接到第二反相器的输出端和第一反相器的输入端。

公开(公告)号：US09318318B1

公开(公告)日：2016-04-19

申请号：US14589022

申请日：2015-01-05

申请人： International Business Machines Corporation

发明人： Kevin K. Chan ,  Pouya Hashemi ,  Effendi Leobandung ,  Dae-Gyu Park ,  Min Yang

IPC分类号： H01L21/22 ,  H01L21/38 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

CPC分类号： H01L29/785 ,  H01L29/66553 ,  H01L29/66803 ,  H01L29/66848 ,  H01L29/7848

摘要： A method for fabricating a semiconductor device includes receiving a gated finned substrate comprising an isolation layer with a semiconductor fin formed thereon and a gate formed over the semiconductor fin, depositing an atomic layer of dopant on a portion of the semiconductor fin that is laterally adjacent to the gate, forming a lateral spacer on a sidewall of the gate and above a gate extension portion of the atomic layer of dopant, and epitaxially growing a raised source or drain region on the semiconductor fin, that is laterally adjacent to the lateral spacer, from the atomic layer of dopant. The method may also include conducting a low temperature annealing process to diffuse the atomic layer of dopant to the raised source or drain region of the semiconductor fin. A corresponding apparatus is also disclosed herein.

摘要翻译： 一种用于制造半导体器件的方法，包括接收包括形成在其上的半导体鳍片的隔离层和形成在半导体鳍片上的栅极的栅极翅片衬底，在半导体鳍片的横向相邻的部分上沉积掺杂剂原子层 所述栅极在所述栅极的侧壁上形成侧向间隔物，并且在所述掺杂剂原子层的栅极延伸部分上方，并且在所述半导体鳍片上外延生长与所述侧向间隔物横向相邻的凸起的源极或漏极区域， 掺杂剂的原子层。 该方法还可以包括进行低温退火工艺以将掺杂剂的原子层扩散到半导体鳍片的升高的源极或漏极区域。 本文还公开了相应的装置。

公开(公告)号：US09209276B2

公开(公告)日：2015-12-08

申请号：US14165120

申请日：2014-01-27

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shun-ichi Nakamura ,  Yasuyuki Kawada

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/308 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/47

CPC分类号： H01L29/66666 ,  H01L21/02378 ,  H01L21/0337 ,  H01L21/265 ,  H01L21/28008 ,  H01L21/308 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66522 ,  H01L29/66848 ,  H01L29/7806 ,  H01L29/7813

摘要： A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The intersection trench intersecting the gate trench is provided so as to be deeper than the gate trench. A Schottky electrode is provided in the bottom of each intersection trench 10p. In this manner, there is provided a trench gate type semiconductor device and a method of producing the same, in which: the cell pitch can be reduced even when a wide band gap semiconductor is used as a main semiconductor substrate; good ohmic contacts can be obtained; and an excessive electric field is prevented from being applied to an insulating film in the bottom of each trench.

摘要翻译： 提供了一种制造沟槽栅型MOSFET的方法，其中每个交叉沟槽形成为两级沟槽结构。 用掩模材料回填栅极沟槽，然后对掩模材料进行构图以形成用于形成每个交叉沟槽的掩模。 与栅极沟槽交叉的交叉沟槽设置成比栅极沟深。 在每个交叉沟槽10p的底部设置肖特基电极。 以这种方式，提供了沟槽栅型半导体器件及其制造方法，其中：即使当使用宽带隙半导体作为主半导体衬底时，也可以减小电池间距; 可以获得良好的欧姆接触; 并且防止了过量的电场被施加到每个沟槽的底部中的绝缘膜。

公开(公告)号：US20150349097A1

公开(公告)日：2015-12-03

申请号：US14822267

申请日：2015-08-10

申请人： Infineon Technologies AG

发明人： Jens Konrath ,  Hans-Joachim Schulze ,  Roland Rupp ,  Wolfgang Werner ,  Frank Pfirsch

IPC分类号： H01L29/66

CPC分类号： H01L29/66909 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66431 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/8122 ,  H01L29/872

摘要： A method for forming a field-effect semiconductor device includes: providing a wafer having a main surface and a first semiconductor layer of a first conductivity type; forming at least two trenches from the main surface partly into the first semiconductor layer so that each of the at least two trenches includes, in a vertical cross-section substantially orthogonal to the main surface, a side wall and a bottom wall, and that a semiconductor mesa is formed between the side walls of the at least two trenches; forming at least two second semiconductor regions of a second conductivity type in the first semiconductor layer so that the bottom wall of each of the at least two trenches adjoins one of the at least two second semiconductor regions; and forming a rectifying junction at the side wall of at least one of the at least two trenches.

摘要翻译： 一种形成场效应半导体器件的方法包括：提供具有第一导电类型的主表面和第一半导体层的晶片; 从所述主表面形成至少两个沟槽部分地进入所述第一半导体层，使得所述至少两个沟槽中的每一个在基本上垂直于所述主表面的垂直横截面中包括侧壁和底壁，并且 在所述至少两个沟槽的侧壁之间形成半导体台面; 在所述第一半导体层中形成具有第二导电类型的至少两个第二半导体区域，使得所述至少两个沟槽中的每一个的底壁与所述至少两个第二半导体区域中的一个相邻; 以及在所述至少两个沟槽中的至少一个的侧壁的侧壁上形成整流结。

公开(公告)号：US09064904B2

公开(公告)日：2015-06-23

申请号：US14308929

申请日：2014-06-19

申请人： PFC DEVICE CORP.

发明人： Hung-Hsin Kuo

IPC分类号： H01L21/28 ,  H01L21/44 ,  H01L29/66 ,  H01L29/739 ,  H01L29/872 ,  H01L29/06

CPC分类号： H01L29/66848 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/66143 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/872

摘要： A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.

摘要翻译： MOS PN结肖特基二极管器件包括具有第一导电类型的衬底，限定沟槽结构的场氧化物结构，形成在沟槽结构中的栅极结构以及与衬底中的栅极结构相邻的具有第二导电类型的掺杂区 。 在栅极结构的不同侧形成欧姆接触和肖特基接触。 制造这种二极管器件的方法包括几个离子注入步骤，以形成具有不同注入深度的多个掺杂子区域以构成掺杂区域。 形成的MOS P-N结肖特基二极管器件具有低正向压降，低反向漏电流，快速反向恢复时间和高反向电压容限。