公开(公告)号：US20070170469A1

公开(公告)日：2007-07-26

申请号：US11337147

申请日：2006-01-20

申请人： Kuo-Ming Wu ,  Jian-Hsing Lee ,  Yi-Chun Lin ,  Chi-Chih Chen

发明人： Kuo-Ming Wu ,  Jian-Hsing Lee ,  Yi-Chun Lin ,  Chi-Chih Chen

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/4238

摘要： A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.

摘要翻译： 半导体器件包括设置在半导体衬底中的第一阱上的第一掺杂区; 第二掺杂区域，其设置在与所述半导体衬底中的所述第一阱相邻的第二阱上，所述第二掺杂区域的掺杂剂密度高于所述第二阱的掺杂剂密度; 以及覆盖第一和第二阱的部分的栅极结构，用于控制在第一和第二掺杂区域之间流动的电流。 从第二掺杂区域和第二阱之间的界面到其栅极结构的最近边缘的第一间隔距离大于从第二掺杂区域的中心点到栅极结构边缘的第二间隔距离的200％ 从而增加针对在ESD事件期间在第一和第二掺杂区域之间流动的静电放电（ESD）电流的阻抗。

公开(公告)号：US07420252B2

公开(公告)日：2008-09-02

申请号：US11337147

申请日：2006-01-20

申请人： Kuo-Ming Wu ,  Jian-Hsing Lee ,  Yi-Chun Lin ,  Chi-Chih Chen

发明人： Kuo-Ming Wu ,  Jian-Hsing Lee ,  Yi-Chun Lin ,  Chi-Chih Chen

IPC分类号： H01L23/62

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/4238

摘要： A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.

摘要翻译： 半导体器件包括设置在半导体衬底中的第一阱上的第一掺杂区; 第二掺杂区域，其设置在与所述半导体衬底中的所述第一阱相邻的第二阱上，所述第二掺杂区域的掺杂剂密度高于所述第二阱的掺杂剂密度; 以及覆盖第一和第二阱的部分的栅极结构，用于控制在第一和第二掺杂区域之间流动的电流。 从第二掺杂区域和第二阱之间的界面到其栅极结构的最近边缘的第一间隔距离大于从第二掺杂区域的中心点到栅极结构边缘的第二间隔距离的200％ 从而增加针对在ESD事件期间在第一和第二掺杂区域之间流动的静电放电（ESD）电流的阻抗。

公开(公告)号：US07602037B2

公开(公告)日：2009-10-13

申请号：US11692213

申请日：2007-03-28

申请人： Yi-Chun Lin ,  Chi-Chih Chen ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

发明人： Yi-Chun Lin ,  Chi-Chih Chen ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

IPC分类号： H01L27/088 ,  H01L29/06

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

摘要： An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region.

摘要翻译： 能够进行高压操作的半导体器件的示例性实施例包括其中具有阱区的衬底。 具有与其相对的第一侧和第二侧的栅极堆叠覆盖在阱区域上。 在阱区内，掺杂体区域包括在栅叠层的一部分下延伸的沟道区，漂移区与沟道区相邻。 漏极区域在漂移区域内并与其第一侧隔开距离，并且源极区域在其第二侧附近的掺杂体区域内。 在掺杂体区和阱区之间不存在P-N结。

公开(公告)号：US20080237703A1

公开(公告)日：2008-10-02

申请号：US11692213

申请日：2007-03-28

申请人： Yi-Chun Lin ,  Chi-Chih Chen ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

发明人： Yi-Chun Lin ,  Chi-Chih Chen ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

摘要： An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region.

摘要翻译： 能够进行高压操作的半导体器件的示例性实施例包括其中具有阱区的衬底。 具有与其相对的第一侧和第二侧的栅极堆叠覆盖在阱区域上。 在阱区内，掺杂体区域包括在栅叠层的一部分下延伸的沟道区，漂移区与沟道区相邻。 漏极区域在漂移区域内并与其第一侧隔开距离，并且源极区域在其第二侧附近的掺杂体区域内。 在掺杂体区和阱区之间不存在P-N结。

公开(公告)号：US20080191276A1

公开(公告)日：2008-08-14

申请号：US11703678

申请日：2007-02-08

申请人： Chi-Chih Chen ,  Yi-Chun Lin ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

发明人： Chi-Chih Chen ,  Yi-Chun Lin ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/66689 ,  H01L21/26586 ,  H01L29/7816

摘要： Semiconductor devices and fabrication methods thereof. The semiconductor device includes a semiconductor substrate with a body region of a first doping type. A gate structure is patterned on the semiconductor substrate. A single spacer is formed on a first sidewall of the gate structure. A body region of a first doping type is formed in the semiconductor substrate adjacent to a second sidewall of the gate structure. A source region of a second doping type is formed on the body region and having an edge aligned with the second sidewall of the gate structure. A drain region of the second doping type is formed on the semiconductor substrate and having an edge aligned with an exterior surface of the single sidewall.

摘要翻译： 半导体器件及其制造方法。 半导体器件包括具有第一掺杂类型的体区的半导体衬底。 在半导体衬底上构图栅极结构。 在栅极结构的第一侧壁上形成单个间隔物。 第一掺杂类型的体区形成在与栅极结构的第二侧壁相邻的半导体衬底中。 第二掺杂类型的源极区域形成在主体区域上并且具有与栅极结构的第二侧壁对准的边缘。 第二掺杂类型的漏极区域形成在半导体衬底上并且具有与单个侧壁的外表面对准的边缘。

公开(公告)号：US07781834B2

公开(公告)日：2010-08-24

申请号：US11773364

申请日：2007-07-03

申请人： Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

发明人： Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

IPC分类号： H01L29/78 ,  H01L29/10

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878

摘要： A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width.

摘要翻译： 半导体器件包括在半导体衬底上的栅电极，其中栅电极具有栅极宽度方向; 在所述半导体衬底中并且与所述栅电极相邻的源极/漏极区域，其中所述源极/漏极区域在平行于所述栅极宽度方向的方向上具有第一宽度; 以及半导体衬底中的块体拾取区域并且邻接源极/漏极区域。 本体拾取区域和源极/漏极区域具有相反的导电类型。 本体拾取区域在宽度方向上具有第二宽度，并且其中第二宽度基本上小于第一宽度。

公开(公告)号：US20090008710A1

公开(公告)日：2009-01-08

申请号：US11773364

申请日：2007-07-03

申请人： Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

发明人： Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878

摘要： A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width.

摘要翻译： 半导体器件包括在半导体衬底上的栅电极，其中栅电极具有栅极宽度方向; 在所述半导体衬底中并且与所述栅电极相邻的源极/漏极区域，其中所述源极/漏极区域在平行于所述栅极宽度方向的方向上具有第一宽度; 以及半导体衬底中的块体拾取区域并且邻接源极/漏极区域。 本体拾取区域和源极/漏极区域具有相反的导电类型。 本体拾取区域在宽度方向上具有第二宽度，并且其中第二宽度基本上小于第一宽度。

公开(公告)号：US08236642B2

公开(公告)日：2012-08-07

申请号：US12910591

申请日：2010-10-22

申请人： Chi-San Wei ,  Kuo-Ming Wu ,  Yi-Chun Lin

发明人： Chi-San Wei ,  Kuo-Ming Wu ,  Yi-Chun Lin

IPC分类号： H01L21/02

CPC分类号： H01L29/1083 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.

摘要翻译： 半导体结构包括半导体衬底; 从半导体衬底的顶表面延伸到半导体衬底中的n型桶，其中n型桶包括埋在半导体衬底中的底部; 在桶的底部设置p型掩埋层（PBL），其中p型掩埋层埋在半导体衬底中; 和高压n型金属氧化物半导体（HVNMOS）器件，并且在由n型槽的侧面包围的区域内。

公开(公告)号：US08022446B2

公开(公告)日：2011-09-20

申请号：US11778525

申请日：2007-07-16

申请人： Wan-Hua Huang ,  Kuo-Ming Wu ,  Yi-Chun Lin ,  Ming Xiang Li

发明人： Wan-Hua Huang ,  Kuo-Ming Wu ,  Yi-Chun Lin ,  Ming Xiang Li

IPC分类号： H01L29/78

CPC分类号： H01L29/782 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402

摘要： A semiconductor structure includes a semiconductor substrate; a first well region of a first conductivity type in the semiconductor substrate; a metal-containing layer on the first well region, wherein the metal-containing layer and the first well region form a Schottky barrier; and a first heavily doped region of the first conductivity type in the first well region, wherein the first heavily doped region is horizontally spaced apart from the metal-containing layer.

摘要翻译： 半导体结构包括半导体衬底; 半导体衬底中的第一导电类型的第一阱区; 所述第一阱区域上的含金属层，其中所述含金属层和所述第一阱区形成肖特基势垒; 以及第一阱区中的第一导电类型的第一重掺杂区，其中第一重掺杂区与水分离金属层。

公开(公告)号：US20110039387A1

公开(公告)日：2011-02-17

申请号：US12910591

申请日：2010-10-22

申请人： Chi-San Wei ,  Kuo-Ming Wu ,  Yi-Chun Lin

发明人： Chi-San Wei ,  Kuo-Ming Wu ,  Yi-Chun Lin

IPC分类号： H01L21/336

CPC分类号： H01L29/1083 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.

摘要翻译： 半导体结构包括半导体衬底; 从半导体衬底的顶表面延伸到半导体衬底中的n型桶，其中n型桶包括埋在半导体衬底中的底部; 在桶的底部设置p型掩埋层（PBL），其中p型掩埋层埋在半导体衬底中; 和高压n型金属氧化物半导体（HVNMOS）器件，并且在由n型槽的侧面包围的区域内。