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公开(公告)号:US08576611B2
公开(公告)日:2013-11-05
申请号:US12832320
申请日:2010-07-08
申请人: Kuoyuan (Peter) Hsu , Yukit Tang , Derek Tao , Young Seog Kim
发明人: Kuoyuan (Peter) Hsu , Yukit Tang , Derek Tao , Young Seog Kim
IPC分类号: G11C11/00
CPC分类号: G11C11/419 , G11C7/00 , G11C11/413 , H01L27/11
摘要: Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node.
摘要翻译: 一些实施例涉及一种存储器阵列,包括:布置成多行和多列的多个存储单元; 其中所述多列的列包括列接地节点; 至少两个电压源被配置为选择性地耦合到所述列接地节点; 以及多个存储单元,其具有电耦合在一起并连接到列地接地节点的多个内部接地节点
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公开(公告)号:US08305827B2
公开(公告)日:2012-11-06
申请号:US12835197
申请日:2010-07-13
申请人: Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
发明人: Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
IPC分类号: G11C5/14
CPC分类号: G11C5/14
摘要: A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, and a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes are electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要翻译: 存储器阵列包括以多行和多列布置的多个存储单元。 多列的列包括被配置为提供第一电压的第一电源节点,被配置为提供第二电压的第二电源节点和电耦合在一起并被配置为接收第一电压的多个内部供电节点, 该列中的多个存储单元的第二电压和多个内部接地节点。 内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。
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公开(公告)号:US08339890B2
公开(公告)日:2012-12-25
申请号:US12788860
申请日:2010-05-27
申请人: Kuoyuan (Peter) Hsu , Yukit Tang , Jacklyn Chang
发明人: Kuoyuan (Peter) Hsu , Yukit Tang , Jacklyn Chang
IPC分类号: G11C5/14
CPC分类号: G11C5/148 , G11C11/413
摘要: A circuit with leakage and data retention control includes at least one memory cell in a first memory array. The at least one memory cell is coupled to a first power supply voltage and a virtual ground. The circuit includes a current source and an NMOS transistor. The drain of the NMOS transistor is coupled to the virtual ground and the gate of the NMOS transistor is coupled to the current source.
摘要翻译: 具有泄漏和数据保持控制的电路包括第一存储器阵列中的至少一个存储单元。 所述至少一个存储单元耦合到第一电源电压和虚拟地。 该电路包括电流源和NMOS晶体管。 NMOS晶体管的漏极耦合到虚拟接地,并且NMOS晶体管的栅极耦合到电流源。
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公开(公告)号:US08964492B2
公开(公告)日:2015-02-24
申请号:US13560461
申请日:2012-07-27
申请人: Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
发明人: Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
CPC分类号: G11C7/222 , G11C7/12 , G11C7/227 , G11C11/419
摘要: A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.
摘要翻译: 电路包括跟踪写入电路和写入电路。 基于跟踪写入电路的跟踪信号产生写入电路的各种写入信号。 写信号用于存储单元的写入操作。
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公开(公告)号:US08929154B2
公开(公告)日:2015-01-06
申请号:US13267235
申请日:2011-10-06
申请人: Jacklyn Chang , Derek C. Tao , Yukit Tang , Kuoyuan (Peter) Hsu
发明人: Jacklyn Chang , Derek C. Tao , Yukit Tang , Kuoyuan (Peter) Hsu
IPC分类号: G11C7/10 , G11C7/18 , H01L27/02 , G11C11/412 , G11C11/413 , H01L27/11
CPC分类号: G11C7/18 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/1104
摘要: A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
摘要翻译: 半导体结构包括第一带状电池,第一读取端口和第一VSS端子。 第一带状电池具有第一带电池VSS区域。 第一读取端口具有第一读取端口VSS区域,第一读取端口读取位线区域和第一读取端口聚合区域。 第一VSS端子被配置为电耦合第一带电池VSS区域和第一读取端口VSS区域。
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公开(公告)号:US20140032871A1
公开(公告)日:2014-01-30
申请号:US13560461
申请日:2012-07-27
申请人: Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
发明人: Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
CPC分类号: G11C7/222 , G11C7/12 , G11C7/227 , G11C11/419
摘要: A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.
摘要翻译: 电路包括跟踪写入电路和写入电路。 基于跟踪写入电路的跟踪信号产生写入电路的各种写入信号。 写信号用于存储单元的写入操作。
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公开(公告)号:US08913440B2
公开(公告)日:2014-12-16
申请号:US13253749
申请日:2011-10-05
IPC分类号: G11C7/10 , G11C11/419
CPC分类号: G11C7/222 , G11C7/10 , G11C7/1051 , G11C11/419
摘要: A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.
摘要翻译: 跟踪信号的跟踪边缘被激活。 基于跟踪信号的跟踪边缘,缓冲器被关闭并且锁存电路被接通。 缓冲器的缓冲器输出耦合到节点处的锁存电路的锁存器输出。 缓冲区接收一个内存宏的数据行。
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公开(公告)号:US08605523B2
公开(公告)日:2013-12-10
申请号:US13399877
申请日:2012-02-17
IPC分类号: G11C7/00
CPC分类号: G11C29/24 , G11C7/222 , G11C11/41 , G11C29/50012 , G11C2029/5002
摘要: A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.
摘要翻译: 确定时间延迟以覆盖具有跟踪电路的存储器宏中的存储器单元的定时。 基于时间延迟,确定与时间延迟相对应的电容。 使用具有确定的电容的电容器。 电容器耦合到跟踪电路的跟踪单元的第一数据线。 第一数据线的第一转变导致存储器单元的第二数据线的第一转变。
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公开(公告)号:US08587991B2
公开(公告)日:2013-11-19
申请号:US13429082
申请日:2012-03-23
CPC分类号: G11C11/412
摘要: A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要翻译: 电路包括第一节点; 第二个节点; 具有耦合到第一节点的源极的第一PMOS晶体管,耦合到第一控制晶体管的漏极和由第一电压驱动的栅极; 以及第一NMOS晶体管,其具有耦合到第二节点的源极,耦合到第一控制晶体管的漏极和由第二电压驱动的栅极。 第一PMOS晶体管被配置为基于第一节点处的第一电压和第一节点电压自动关闭。 第一NMOS晶体管被配置为基于第二节点处的第二电压和第二节点电压自动关闭。 当第一PMOS晶体管,控制晶体管和第一NMOS晶体管导通时,第一节点电压降低,而第二电压升高。
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公开(公告)号:US08159862B2
公开(公告)日:2012-04-17
申请号:US12843366
申请日:2010-07-26
CPC分类号: G11C11/412
摘要: A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要翻译: 电路包括第一节点; 第二个节点; 具有耦合到第一节点的源极的第一PMOS晶体管,耦合到第一控制晶体管的漏极和由第一电压驱动的栅极; 以及第一NMOS晶体管,其具有耦合到第二节点的源极,耦合到第一控制晶体管的漏极和由第二电压驱动的栅极。 第一PMOS晶体管被配置为基于第一节点处的第一电压和第一节点电压自动关闭。 第一NMOS晶体管被配置为基于第二节点处的第二电压和第二节点电压自动关闭。 当第一PMOS晶体管,控制晶体管和第一NMOS晶体管导通时,第一节点电压降低,而第二电压升高。
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