公开(公告)号：US5304871A

公开(公告)日：1994-04-19

申请号：US919605

申请日：1992-07-24

申请人： Kuthanur R. Dharmarajan ,  Khaled A. El-Ayat ,  Gregory W. Bakker

发明人： Kuthanur R. Dharmarajan ,  Khaled A. El-Ayat ,  Gregory W. Bakker

IPC分类号： G11C17/00 ,  G11C17/16 ,  H01L27/10 ,  H03K19/177

CPC分类号： H03K19/17736 ,  G11C17/16 ,  H03K19/17704 ,  H03K19/1778

摘要： Apparatus for terminating unused input lines in a user-programmable interconnect architecture to one of a first voltage potential and a second voltage potential comprises at least one first tie-off conductor divided into at least two first segments and insulated from and intersecting the input lines, and at least one second tie-off conductor divided into at least two second segments and insulated from and intersecting the input lines. A plurality of first termination transistors each have their drains connected to a voltage rail for the first voltage potential and their sources connected to a different one of the first segments. A plurality of second termination transistors each have their sources connected to a voltage rail for the first voltage potential and their drains connected to a different one of the second segments. A termination transistor gate line is connected to the gates of each of the first and second termination transistors. A plurality of programming transistors each has its source connected to a different one of the first and second segments and its drain connected to a circuit which supplies a programming potential. A programming transistor gate line is connected to the gates of each of the programming transistors. Programming circuitry is connected to the programming transistor gate line, and is used to selectively turn on the gates of the programming transistors during a programming operation, and to selectively connect a programming voltage potential to the drain of a selected programming transistor while simultaneously connecting a potential substantially equal to one half of said programming voltage potential to the drains of all other programming transistors. Operation enable circuitry is connected to the first and second termination transistor gate line to connect the first and second segments to the first and second voltage potentials during circuit operation.

摘要翻译： 用于将用户可编程互连架构中的未使用输入线路终止于第一电压电位和第二电压电位之一的装置包括分成至少两个第一部分并与输入线绝缘并与之相交的至少一个第一断开导体， 以及分成至少两个第二段并且与输入线绝缘并与其相交的至少一个第二触发导体。 多个第一端接晶体管各自的漏极连接到用于第一电压电位的电压轨，并且其源极连接到不同的第一段。 多个第二终端晶体管各自的源极连接到用于第一电压电位的电压轨，并且其漏极连接到不同的第二段。 端接晶体管栅极线连接到第一和第二端接晶体管中的每一个的栅极。 多个编程晶体管的源极连接到第一和第二段中的不同的一个，其漏极连接到提供编程电位的电路。 编程晶体管栅极线连接到每个编程晶体管的栅极。 编程电路连接到编程晶体管栅极线，并且用于在编程操作期间选择性地导通编程晶体管的栅极，并且选择性地将编程电压电位连接到所选择的编程晶体管的漏极，同时连接电位 基本上等于所有其他编程晶体管的漏极的所述编程电压电位的一半。 操作使能电路连接到第一和第二终端晶体管栅极线，以在电路操作期间将第一和第二段连接到第一和第二电压电位。

公开(公告)号：US5194759A

公开(公告)日：1993-03-16

申请号：US835221

申请日：1992-02-13

申请人： Khaled A. El-Ayat ,  Kenneth D. Hayes ,  Theodore M. Speers ,  Gregory W. Bakker

发明人： Khaled A. El-Ayat ,  Kenneth D. Hayes ,  Theodore M. Speers ,  Gregory W. Bakker

IPC分类号： G11C17/18

CPC分类号： G11C17/18

摘要： A method to minimize disturbance of an already programmed antifuse while programming other antifuses in a circuit includes the steps of determining a preferred order in which to program the antifuses and programming them in the preferred order. High initial programming and soak currents are selected such that the disturb current is small with respect thereto. The magnitude of the disturb current is increased to a value that maintains the antifuse resistance or improves it rather than adversely affect it. Where a circuit node containing a first already programmed antifuse is positioned such that parasitic capacitances may discharge through that antifuse during the programming of a second antifuse, the magnitude of the charge stored at parasitic capacitances associated with the programming path is reduced by reducing the programming voltage when this programming situation is detected. After the initial rupturing of the antifuse dielectric is detected, the programming voltage is increased to its normal value for the soaking period.

摘要翻译： 一种在编程电路中的其它反熔丝的同时最小化对已编程的反熔丝的干扰的方法包括以优选顺序确定编程反熔丝并优化其顺序的优选顺序的步骤。 选择高初始编程和浸泡电流，使得干扰电流相对于其小。 干扰电流的大小增加到维持反熔丝电阻或提高反熔点的值，而不是不利地影响它。 在包含第一已经编程的反熔丝的电路节点被定位成使得寄生电容可以在编程第二反熔丝期间通过该反熔丝放电时，通过减少编程电压来减小存储在与编程路径相关联的寄生电容处的电荷的大小 当该编程情况被检测到时。 在检测到反熔丝电介质的初始断裂之后，编程电压在均热期间增加到正常值。

公开(公告)号：US5600265A

公开(公告)日：1997-02-04

申请号：US575519

申请日：1995-12-20

申请人： Abbas El Gamal ,  Khaled A. El-Ayat ,  Amr Mohsen

发明人： Abbas El Gamal ,  Khaled A. El-Ayat ,  Amr Mohsen

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L25/00 ,  H03K19/177

CPC分类号： G01R31/2884 ,  G01R31/318516 ,  G01R31/318519 ,  H03K19/17704 ,  H03K19/17736

摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

摘要翻译： 公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。 在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。 接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。 接线通道包括通过常开可编程连接的接线段。 位于要连接的任何两个段的交点处的元素。

公开(公告)号：US5365165A

公开(公告)日：1994-11-15

申请号：US889839

申请日：1992-05-26

申请人： Khaled A. El-Ayat ,  Jia-Hwang Chang

发明人： Khaled A. El-Ayat ,  Jia-Hwang Chang

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H03K19/177 ,  G01R31/02

CPC分类号： H03K19/17764 ,  G01R31/2884 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17744

摘要： An integrated circuit having a plurality of input/output modules, each of which has input/output modules including an input module section having an input node connected to a unique input/output pin on the integrated circuit and an output node communicating with a unique first internal node in the integrated circuit, and an output module section having an input node communicating with a unique second internal node in the integrated circuit and an output node communicating with the unique input/output pin. Each input/output module is programmable by a user such that its function may be defined as an input module, an output module, or a bi-directional module. The integrated circuit further has two states, a first unprogrammed state where none of the functions of the input/output modules have been defined, and a second, programmed state in which the functions of the input/output modules have been defined by either enabling or disabling the output section of the input/output module. Circuitry for testing the input module section of one of the input/output modules in the unprogrammed state comprises means for temporarily disabling the output section of a unique one of the input/output modules, means for temporarily connecting the output node of the input module section to a test node on said integrated circuit, and means for communicating the state of the test node to a test input/output pin on the integrated circuit.

摘要翻译： 一种具有多个输入/输出模块的集成电路，每个输入/输出模块具有输入/输出模块，该输入/输出模块包括具有连接到集成电路上的唯一输入/输出引脚的输入节点的输入模块部分和与唯一的第一 集成电路中的内部节点以及具有与集成电路中唯一的第二内部节点通信的输入节点的输出模块部分和与唯一输入/输出引脚通信的输出节点。 每个输入/输出模块可由用户编程，使得其功能可被定义为输入模块，输出模块或双向模块。 集成电路还具有两个状态，即未定义输入/输出模块的功能的第一未编程状态，以及第二编程状态，其中输入/输出模块的功能已被定义为启用或 禁用输入/输出模块的输出部分。 用于在未编程状态下测试其中一个输入/输出模块的输入模块部分的电路包括用于临时禁用输入/输出模块中唯一一个的输出部分的装置，用于临时连接输入模块部分的输出节点的装置 到所述集成电路上的测试节点，以及用于将所述测试节点的状态传送到所述集成电路上的测试输入/输出引脚的装置。

公开(公告)号：US5309091A

公开(公告)日：1994-05-03

申请号：US822490

申请日：1992-01-14

申请人： Khaled A. El-Ayat ,  Jia-Hwang Chang

发明人： Khaled A. El-Ayat ,  Jia-Hwang Chang

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H03K19/177 ,  G01R31/02

CPC分类号： G01R31/2884 ,  G01R31/318516 ,  H03K19/17704

摘要： In a user-configurable integrated circuit including a plurality of uncommitted conductors which may be programmably connected to one another and to functional circuit blocks by a user to form electronic circuits, apparatus for testing for defects in the form of breaks in the electrical continuity of individual ones of the conductors prior to formation of the electronic circuits by a user, including circuitry responsive to external signals for temporarily connecting together selected ones of the uncommitted conductors to form a series circuit having a first end conductor and a second end conductor, circuitry for placing an electrical charge on the first end conductor such that a selected dynamic voltage is placed on the first end conductor, circuitry for driving the second end conductor to a voltage different from the selected dynamic voltage, circuitry for sensing the voltage on the first end conductor at a predetermined time after the driving voltage has been removed, circuitry for storing a signal related to the sensed voltage on the first end conductor, and circuitry for communicating the signal to an input/output pad of the integrated circuit.

摘要翻译： 在用户可配置的集成电路中，包括可以可编程地彼此连接的多个未提交的导体和由用户形成电子电路的功能电路块，用于测试个体电连续性中的断裂形式的缺陷的装置 由用户形成电子电路之前的导​​体中的一个，包括响应于外部信号的电路，用于将未提交的导体临时连接在一起以形成具有第一端导体和第二端导体的串联电路，用于放置的电路 在第一端部导体上的电荷，使得选择的动态电压被放置在第一端部导体上，用于将第二端部导体驱动到与选择的动态电压不同的电压的电路，用于感测第一端部导体上的电压的电路 在驱动电压被去除之后的预定时间， 将与第一端部导体上的检测到的电压相关的信号，以及用于将该信号传送到集成电路的输入/输出焊盘的电路。

公开(公告)号：US5223792A

公开(公告)日：1993-06-29

申请号：US891969

申请日：1992-05-26

申请人： Khaled A. El-Ayat ,  Jia-Hwang Chang

发明人： Khaled A. El-Ayat ,  Jia-Hwang Chang

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H03K19/177

CPC分类号： H03K19/17764 ,  G01R31/2884 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/1778

摘要： Apparatus for testing for defects in the form of ohmic leakage in an antifuse element disposed between first and second conductors in an integrated circuit prior to formation of electronic circuits by a user, includes circuitry, responsive to signals provided to the integrated circuit from an external source, for temporarily connecting together a first group of the conductors to form a circuit path to the first conductor during a first time period. Circuitry, responsive to signals provided to the integrated circuit from an external source, is provided to temporarily connect together a second group of the conductors to form a circuit path to the second conductor during the first time period. Circuitry is provided to place an electrical charge onto the first conductor during a second time period within the first time period such that a selected dynamic first voltage potential is placed on the first conductor. Circuitry is provided to drive the second conductor to a second voltage potential different from the selected dynamic first voltage potential during a third time period subsequent to the second time period and within the first time period, wherein the difference between the first voltage potential and the second voltage potential is less than the voltage necessary to cause degradation of the antifuse element. Circuitry is provided to sense the voltage on the first conductor at a predetermined time after the start of the third time period and within the first time period. Circuitry is provided to store a signal related to the voltage on the first conductor at the predetermined time after the start of the third time period. Circuitry is provided to communicate the signal to an input/output pad of the integrated circuit.

摘要翻译： 用于在由用户形成电子电路之前在集成电路中设置在集成电路中的第一和第二导体之间的反熔丝元件中的欧姆泄漏形式的缺陷测试的装置包括响应于从外部源提供给集成电路的信号的电路 用于在第一时间段期间将第一组导体临时连接在一起以形成到第一导体的电路。 提供响应于从外部源提供给集成电路的信号的电路，用于将第二组导体临时连接在一起，以在第一时间段内形成到第二导体的电路。 提供电路以在第一时间段内的第二时间段内将电荷置于第一导体上，使得选择的动态第一电压电位置于第一导体上。 提供电路以在第二时间段之后的第三时间段内并在第一时间段内将第二导体驱动到与所选择的动态第一电压电位不同的第二电压电位，其中第一电压电势与第二电压之间的差 电压电位小于导致反熔丝元件劣化所需的电压。 提供电路以在第三时间段开始之后的预定时间并且在第一时间段内感测第一导体上的电压。 提供电路以在第三时间段开始之后的预定时间存储与第一导体上的电压有关的信号。 提供电路以将信号传送到集成电路的输入/输出焊盘。

公开(公告)号：US4758745A

公开(公告)日：1988-07-19

申请号：US909261

申请日：1986-09-19

申请人： Abbas Elgamal ,  Khaled A. El-Ayat ,  Amr Mohsen

发明人： Abbas Elgamal ,  Khaled A. El-Ayat ,  Amr Mohsen

IPC分类号： G01R31/3185 ,  H03K19/177 ,  H03K17/693

CPC分类号： H03K19/17748 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17796

摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface.

摘要翻译： 公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。 在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。 接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。 布线通道包括通过常开的可编程元件连接的布线段，所述可编程元件位于要连接的任何两个段的交点处。 可以包括感应电路和接线，以允许来自外部接口接口的内部电路节点（如模块输出）的100％可观察性。

公开(公告)号：US06617875B2

公开(公告)日：2003-09-09

申请号：US10246095

申请日：2002-09-17

申请人： Khaled A. El-Ayat

发明人： Khaled A. El-Ayat

IPC分类号： H03K19177

CPC分类号： H03K19/17748 ,  H03K19/17744 ,  H03K19/1778

摘要： The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards.

摘要翻译： 本发明公开了一种用于FPGA的输入/输出缓冲器部分的架构。 它提供了一种方便有效的寻址方案，用于寻址用于在FPGA中配置可编程输入/输出缓冲器的熔丝矩阵。 可编程I / O缓冲器可以被配置为实现大量不同的输出和输入总线标准。

公开(公告)号：US5625301A

公开(公告)日：1997-04-29

申请号：US444243

申请日：1995-05-18

申请人： William C. Plants ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  King W. Chan ,  Khaled A. El-Ayat

发明人： William C. Plants ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  King W. Chan ,  Khaled A. El-Ayat

IPC分类号： H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/17704

摘要： An input/output architecture for a field-programmable gate array integrated circuit including a plurality of logic function modules in an array of rows and columns, each of the modules having at least one input conductor and at least one output conductor; a plurality of interconnect conductors, comprising a plurality of input/output pads; a plurality of input/output kernels, each input/output kernel comprising an input buffer having a data input connected to one of the I/O pads and a data output connected to an input buffer data conductor, an output buffer having a data input connected to an output buffer data conductor, a data output connected to the I/O pad, and an enable input connected to an output buffer enable conductor; the input buffer data conductors extending in either the row or the column direction, different ones of the input buffer data conductors extending different numbers of rows or columns, the input buffer data conductors forming first intersections with inputs of the modules; the output buffer data conductors and output buffer enable conductors extending in either the row or the column direction, different ones of the output buffer data conductors and output buffer enable conductors extending different numbers of rows or columns, the input buffer data conductors forming second intersections with outputs of the modules; and user-programmable interconnect elements connected across selected ones of the first and second intersections.

摘要翻译： 一种用于现场可编程门阵列集成电路的输入/输出架构，包括行和列阵列中的多个逻辑功能模块，每个模块具有至少一个输入导体和至少一个输出导体; 多个互连导体，包括多个输入/输出焊盘; 多个输入/输出内核，每个输入/输出内核包括输入缓冲器，该输入缓冲器具有连接到I / O焊盘之一的数据输入和连接到输入缓冲器数据导体的数据输出;输出缓冲器，其具有连接的数据输入 连接到输出缓冲器数据导体，连接到I / O焊盘的数据输出和连接到输出缓冲器使能导体的使能输入; 输入缓冲器数据导体在行或列方向上延伸，不同的输入缓冲器数据导体延伸不同数量的行或列，输入缓冲器数据导体与模块的输入形成第一交点; 输出缓冲器数据导体和输出缓冲器使能导体在行或列方向上延伸，不同的输出缓冲器数据导体和输出缓冲器使能导体延伸不同数量的行或列，输入缓冲器数据导体与第 模块输出; 以及连接在第一和第二交叉点中的选定的互连元件之间的用户可编程互连元件。

公开(公告)号：US5432441A

公开(公告)日：1995-07-11

申请号：US102381

申请日：1993-08-05

申请人： Khaled A. El-Ayat ,  Jia-Hwang Chang

发明人： Khaled A. El-Ayat ,  Jia-Hwang Chang

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H03K19/177 ,  G01R31/02

CPC分类号： H03K19/17764 ,  G01R31/2884 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17744

摘要： In an integrated circuit having a plurality of function modules, each of the function modules having at least two inputs and at least one output. The integrated circuit is user programmable such that interconnections between selected ones of the function modules and input/output pins on the integrated circuit may be made. The integrated circuit further having two states, a first unprogrammed state where none of the interconnections have been made, and a second, programmed state in which selected interconnections have been made. Circuitry for testing the functionality of individual ones of the function modules when the integrated circuit is in the unprogrammed state comprises addressing means for selecting any one of the function modules, data input means for providing a selected logic level to at least one of the inputs of the function module selected by the addressing means, and output-connecting means, responsive to the addressing means, for temporarily connecting the output of the selected one of the function modules to one of the input/output pins on the integrated circuit.

摘要翻译： 在具有多个功能模块的集成电路中，每个功能模块具有至少两个输入和至少一个输出。 集成电路是用户可编程的，使得可以制造集成电路上的功能模块中的选定功能模块和输入/输出引脚之间的互连。 集成电路还具有两个状态，即没有进行互连的第一未编程状态，以及已经进行了选择的互连的第二编程状态。 当集成电路处于未编程状态时用于测试各个功能模块的功能的电路包括用于选择任何一个功能模块的寻址装置，用于将所选逻辑电平提供给至少一个输入的数据输入装置 所述功能模块由所述寻址装置选择，以及输出连接装置，响应于所述寻址装置，将所选择的一个所述功能模块的输出临时连接到所述集成电路上的所述输入/输出引脚之一。