SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号:US20120217562A1

    公开(公告)日:2012-08-30

    申请号:US13240873

    申请日:2011-09-22

    Applicant: Kyoung Han LEE

    Inventor: Kyoung Han LEE

    Abstract: A semiconductor device capable of maximizing a channel area in a pillar and a method of manufacturing the same are provided. The semiconductor device includes a pillar disposed on a semiconductor substrate and having first to fourth side surfaces, a first bit line disposed in the first side surface, a storage node junction region disposed in the third side surface facing the first side surface, and a gate disposed in the second side surface or a fourth side surface facing the second surface.

    Abstract translation: 提供一种能够最大化柱中的通道面积的半导体器件及其制造方法。 半导体器件包括设置在半导体衬底上并具有第一至第四侧表面的柱,设置在第一侧表面中的第一位线,设置在面向第一侧表面的第三侧表面中的存储节点结区域和栅极 设置在所述第二侧表面或面向所述第二表面的第四侧表面。

    SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 失效
    包括垂直晶体管的半导体器件及其制造方法

    公开(公告)号:US20120012913A1

    公开(公告)日:2012-01-19

    申请号:US12976792

    申请日:2010-12-22

    Applicant: Kyoung Han LEE

    Inventor: Kyoung Han LEE

    Abstract: A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor disposed over the upper portion of the active region and the word line.

    Abstract translation: 包括垂直晶体管的半导体器件及其制造方法可以减小与8F2和6F2的常规布局相比的单元面积。 此外,该方法不需要形成位线接触,存储节点接触或着陆塞,从而减少处理步骤。 包括垂直晶体管的半导体器件包括:形成在半导体衬底中的有源区; 位于有源区的下部的位线; 埋在活跃区域的字线; 以及设置在有源区域和字线的上部上方的电容器。

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