Abstract:
A semiconductor device capable of maximizing a channel area in a pillar and a method of manufacturing the same are provided. The semiconductor device includes a pillar disposed on a semiconductor substrate and having first to fourth side surfaces, a first bit line disposed in the first side surface, a storage node junction region disposed in the third side surface facing the first side surface, and a gate disposed in the second side surface or a fourth side surface facing the second surface.
Abstract:
A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor disposed over the upper portion of the active region and the word line.