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    ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE
    7.
    发明申请
    ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE 有权
    具有降低功率的高级存储器件和改进的性能

    公开(公告)号：US20100220536A1

    公开(公告)日：2010-09-02

    申请号：US12394804

    申请日：2009-02-27

    申请人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    发明人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C8/12 ,  Y02D10/14

    摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.

    摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。

    Advanced memory device having reduced power and improved performance
    8.
    发明授权
    Advanced memory device having reduced power and improved performance 有权
    具有降低的功率和改进的性能的高级存储器件

    公开(公告)号：US07948817B2

    公开(公告)日：2011-05-24

    申请号：US12394804

    申请日：2009-02-27

    申请人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    发明人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C8/12 ,  Y02D10/14

    摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.

    摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。

    Memory Systems for Automated Computing Machinery
    9.
    发明申请
    Memory Systems for Automated Computing Machinery 有权
    自动计算机存储系统

    公开(公告)号：US20080005496A1

    公开(公告)日：2008-01-03

    申请号：US11383989

    申请日：2006-05-18

    申请人： Daniel M. Dreps ,  Kevin C. Gower ,  Warren E. Maule ,  Robert B. Tremaine

    发明人： Daniel M. Dreps ,  Kevin C. Gower ,  Warren E. Maule ,  Robert B. Tremaine

    IPC分类号： G06F13/00

    CPC分类号： G06F13/1684 ,  G06F13/1673 ,  G06F13/1678 ,  Y02D10/14

    摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.

    摘要翻译： 公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。 出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。 第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。

    Memory systems for automated computing machinery
    10.
    发明授权
    Memory systems for automated computing machinery 有权
    自动计算机的存储系统

    公开(公告)号：US07447831B2

    公开(公告)日：2008-11-04

    申请号：US11383989

    申请日：2006-05-18

    申请人： Daniel M. Dreps ,  Kevin C. Gower ,  Warren E. Maule ,  Robert B. Tremaine

    发明人： Daniel M. Dreps ,  Kevin C. Gower ,  Warren E. Maule ,  Robert B. Tremaine

    IPC分类号： G06F13/14

    CPC分类号： G06F13/1684 ,  G06F13/1673 ,  G06F13/1678 ,  Y02D10/14

    摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.

    摘要翻译： 公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。 出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。 第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。