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    ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE
    1.
    发明申请
    ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE 有权
    具有降低功率的高级存储器件和改进的性能

    公开(公告)号：US20100220536A1

    公开(公告)日：2010-09-02

    申请号：US12394804

    申请日：2009-02-27

    申请人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    发明人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C8/12 ,  Y02D10/14

    摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.

    摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。

    Advanced memory device having reduced power and improved performance
    2.
    发明授权
    Advanced memory device having reduced power and improved performance 有权
    具有降低的功率和改进的性能的高级存储器件

    公开(公告)号：US07948817B2

    公开(公告)日：2011-05-24

    申请号：US12394804

    申请日：2009-02-27

    申请人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    发明人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C8/12 ,  Y02D10/14

    摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.

    摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。

    MEMORY SYSTEM WITH DYNAMIC REFRESHING
    10.
    发明申请
    MEMORY SYSTEM WITH DYNAMIC REFRESHING 有权
    具有动态刷新记忆系统

    公开(公告)号：US20130128682A1

    公开(公告)日：2013-05-23

    申请号：US13298587

    申请日：2011-11-17

    申请人： Joab D. Henderson ,  Hillery C. Hunter ,  Warren E. Maule ,  Jeffrey A. Stuecheli

    发明人： Joab D. Henderson ,  Hillery C. Hunter ,  Warren E. Maule ,  Jeffrey A. Stuecheli

    IPC分类号： G11C11/402

    CPC分类号： G11C11/40611 ,  G11C2211/4061

    摘要： An embodiment provided is a memory system with dynamic refreshing that includes a memory device with memory cells. The system also includes a refresh module in communication with the memory device and with a memory controller, the refresh module configured for receiving a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is responsive to at least one of a desired bandwidth characteristic and a desired latency characteristic.

    摘要翻译： 提供的实施例是具有动态刷新的存储器系统，其包括具有存储器单元的存储器件。 该系统还包括与存储器设备和存储器控制器通信的刷新模块，该刷新模块被配置用于从存储器控制器接收刷新命令，并且响应于接收到所述存储器控制器来刷新存储器设备中的多个存储器单元 刷新命令。 响应于接收到刷新命令刷新的存储器单元的数量响应期望带宽特性和期望延迟特性中的至少一个。