Method of etch model calibration using optical scatterometry

    公开(公告)号:US10572697B2

    公开(公告)日:2020-02-25

    申请号:US15946940

    申请日:2018-04-06

    Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

    METHOD OF ETCH MODEL CALIBRATION USING OPTICAL SCATTEROMETRY

    公开(公告)号:US20200218844A1

    公开(公告)日:2020-07-09

    申请号:US16741735

    申请日:2020-01-13

    Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

    SYSTEM AND METHOD FOR DETERMINING FIELD NON-UNIFORMITIES OF A WAFER PROCESSING CHAMBER USING A WAFER PROCESSING PARAMETER
    3.
    发明申请
    SYSTEM AND METHOD FOR DETERMINING FIELD NON-UNIFORMITIES OF A WAFER PROCESSING CHAMBER USING A WAFER PROCESSING PARAMETER 审中-公开
    使用波浪加工参数确定波浪加工室的现场非均匀性的系统和方法

    公开(公告)号:US20160370796A1

    公开(公告)日:2016-12-22

    申请号:US14860078

    申请日:2015-09-21

    Abstract: A system for controlling a condition of a wafer processing chamber is disclosed. According the principles of the present disclosure, the system includes memory and a first controller. The memory stores a plurality of profiles of respective ones of a plurality of first control elements. The plurality of first control elements are arranged throughout the chamber. The first controller determines non-uniformities in a substrate processing parameter associated with the plurality of first control elements. The substrate processing parameter is different than the condition of the chamber. The first controller adjusts at least one of the plurality of profiles based on the non-uniformities in the substrate processing parameter and a sensitivity of the substrate processing parameter to the condition.

    Abstract translation: 公开了一种用于控制晶片处理室的状态的系统。 根据本公开的原理,系统包括存储器和第一控制器。 存储器存储多个第一控制元件中的各个的多个简档。 多个第一控制元件布置在整个室中。 第一控制器确定与多个第一控制元件相关联的衬底处理参数中的不均匀性。 基板处理参数不同于室的状态。 第一控制器基于衬底处理参数中的不均匀性和衬底处理参数对条件的灵敏度来调整多个轮廓中的至少一个。

    METHOD OF ETCH MODEL CALIBRATION USING OPTICAL SCATTEROMETRY

    公开(公告)号:US20210216695A1

    公开(公告)日:2021-07-15

    申请号:US17301345

    申请日:2021-03-31

    Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

    SYSTEMS AND METHODS FOR PERFORMING EDGE RING CHARACTERIZATION

    公开(公告)号:US20170287682A1

    公开(公告)日:2017-10-05

    申请号:US15403786

    申请日:2017-01-11

    Abstract: A substrate support in a substrate processing system includes an inner portion arranged to support a substrate, an edge ring surrounding the inner portion, and a controller. The controller at least one of lowers the edge ring to selectively cause the edge ring to engage the substrate and raises the inner portion to selectively cause the edge ring to engage the substrate. The controller determines when the edge ring engages the substrate and calculates at least one characteristic of the substrate processing system based on the determination of when the edge ring engages the substrate.

    Methods and systems for controlling wafer fabrication process

    公开(公告)号:US11056405B2

    公开(公告)日:2021-07-06

    申请号:US16131464

    申请日:2018-09-14

    Inventor: Marcus Musselman

    Abstract: A method for controlling a semiconductor fabrication process includes determining a representative feature within a given area on a wafer. The representative feature has a critical dimension (CD) response to a specified process control parameter that is correlated to a CD response to the specified process control parameter of other features within the given area on the wafer. A CD adjustment is determined for the representative feature to achieve a target CD for the representative feature. The CD response to the specified process control parameter for the representative feature and the CD adjustment for the representative feature are used to determine an adjustment to the specified process control parameter that will drive a CD of the representative feature to the target critical dimension for the representative feature. A process controller is updated to implement the adjustment to the specified process control parameter during subsequent processing of another wafer.

    Methods and Systems for Controlling Wafer Fabrication Process

    公开(公告)号:US20200091017A1

    公开(公告)日:2020-03-19

    申请号:US16131464

    申请日:2018-09-14

    Inventor: Marcus Musselman

    Abstract: A method for controlling a semiconductor fabrication process includes determining a representative feature within a given area on a wafer. The representative feature has a critical dimension (CD) response to a specified process control parameter that is correlated to a CD response to the specified process control parameter of other features within the given area on the wafer. A CD adjustment is determined for the representative feature to achieve a target CD for the representative feature. The CD response to the specified process control parameter for the representative feature and the CD adjustment for the representative feature are used to determine an adjustment to the specified process control parameter that will drive a CD of the representative feature to the target critical dimension for the representative feature. A process controller is updated to implement the adjustment to the specified process control parameter during subsequent processing of another wafer.

    METHOD OF ETCH MODEL CALIBRATION USING OPTICAL SCATTEROMETRY

    公开(公告)号:US20190311083A1

    公开(公告)日:2019-10-10

    申请号:US15946940

    申请日:2018-04-06

    Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

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