公开(公告)号：US20150053347A1

公开(公告)日：2015-02-26

申请号：US14470544

申请日：2014-08-27

Applicant: Lam Research Corporation

Inventor： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile.

Abstract translation: 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据。 控制器还接收等离子体室中要处理的当前晶片的关键器件参数。 控制器基于至少一个先前处理的晶片的过程控制和温度数据以及当前晶片的关键器件参数来计算当前晶片的目标修整时间和目标温度分布。 当前的晶片在控制温度控制区域中的温度的同时进行修整操作，同时控制温度控制区域中的温度，从而基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US20140220709A1

公开(公告)日：2014-08-07

申请号：US13758266

申请日：2013-02-04

Applicant: LAM RESEARCH CORPORATION

Inventor： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

Abstract translation: 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据，以及在等离子体室中待处理的当前晶片的关键器件参数。 控制器基于过程控制和温度数据以及关键设备参数来计算当前晶片的目标修整时间和目标温度分布。 在目标修整时间期间修剪当前晶片，同时基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US09012243B2

公开(公告)日：2015-04-21

申请号：US14470544

申请日：2014-08-27

Applicant: Lam Research Corporation

Inventor： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC: H01L21/66 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile.

Abstract translation: 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据。 控制器还接收等离子体室中要处理的当前晶片的关键器件参数。 控制器基于至少一个先前处理的晶片的过程控制和温度数据以及当前晶片的关键器件参数来计算当前晶片的目标修整时间和目标温度分布。 当前的晶片在控制温度控制区域中的温度的同时进行修整操作，同时控制温度控制区域中的温度，从而基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US08852964B2

公开(公告)日：2014-10-07

申请号：US13758266

申请日：2013-02-04

Applicant: Lam Research Corporation

Inventor： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC: H01L21/00 ,  H01L21/67 ,  H01L21/66

CPC classification number: H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

Abstract translation: 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据，以及在等离子体室中待处理的当前晶片的关键器件参数。 控制器基于过程控制和温度数据以及关键设备参数来计算当前晶片的目标修整时间和目标温度分布。 在目标修整时间期间修剪当前晶片，同时基于目标温度分布来控制每个器件管芯位置的温度。