公开(公告)号：US10431426B2

公开(公告)日：2019-10-01

申请号：US15291468

申请日：2016-10-12

Applicant: LAM RESEARCH CORPORATION

Inventor： Tom Kamp ,  Arthur H. Sato ,  Alex Paterson

IPC: H01J37/32 ,  H01L21/3065 ,  H01L21/67

Abstract: A gas plenum arrangement for a substrate processing system includes a gas plenum body arranged to define a gas plenum between a coil and a processing chamber. The coil is arranged outside of an outer edge of the gas plenum body. A plurality of flux attenuating portions is arranged outside of the outer edge of the gas plenum body. The flux attenuation portions overlap the coil.

公开(公告)号：US20170053808A1

公开(公告)日：2017-02-23

申请号：US14830661

申请日：2015-08-19

Applicant: Lam Research Corporation

Inventor： Tom Kamp ,  Neema Rastgar ,  Michael Carl Drymon

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/308

CPC classification number: H01L21/3065 ,  H01J37/32091 ,  H01J37/321 ,  H01J37/3211 ,  H01J37/32449 ,  H01J2237/334 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/67069

Abstract: Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.

Abstract translation: 本文提供了使用包括将半导体衬底的氧化表面暴露于含氟蚀刻气体并加热衬底以通过升华机构去除非挥发性蚀刻副产物的原子层蚀刻工艺横向蚀刻半导体衬底的方法和装置。 方法还包括在脉冲含氟蚀刻气体时额外脉冲含氢气体。 装置还包括适用于分别制备和混合用于各种工具的氨的氨混合歧管。

公开(公告)号：US09484214B2

公开(公告)日：2016-11-01

申请号：US14293547

申请日：2014-06-02

Applicant: Lam Research Corporation

Inventor： Tom Kamp ,  Arthur Sato ,  Alex Paterson

IPC: G01P3/48 ,  H01L21/3065 ,  H01J37/32

CPC classification number: H01J37/3211 ,  H01J37/321 ,  H01J37/32119 ,  H01J37/3244 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/67069

Abstract: A substrate processing system includes a processing chamber including a dielectric window and a pedestal for supporting a substrate during processing. A gas supply system supplies gas to the processing chamber. A coil is arranged outside of the processing chamber adjacent to the dielectric window. A radio frequency (RF) source supplies RF signals to the coil to create RF plasma in the processing chamber. N flux attenuating portions are arranged in a spaced pattern adjacent the coil, wherein N is an integer greater than one.

Abstract translation: 基板处理系统包括处理室，该处理室包括介电窗口和用于在处理期间支撑基板的基座。 气体供应系统向处理室供应气体。 线圈被布置在与介电窗口相邻的处理室的外部。 射频（RF）源向线圈提供RF信号以在处理室中产生RF等离子体。 N个通量衰减部分以与线圈相邻的间隔布置的方式布置，其中N是大于1的整数。

公开(公告)号：US20150235808A1

公开(公告)日：2015-08-20

申请号：US14293547

申请日：2014-06-02

Applicant: Lam Research Corporation

Inventor： Tom Kamp ,  Arthur Sato ,  Alex Paterson

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/3065

CPC classification number: H01J37/3211 ,  H01J37/321 ,  H01J37/32119 ,  H01J37/3244 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/67069

Abstract: A substrate processing system includes a processing chamber including a dielectric window and a pedestal for supporting a substrate during processing. A gas supply system supplies gas to the processing chamber. A coil is arranged outside of the processing chamber adjacent to the dielectric window. A radio frequency (RF) source supplies RF signals to the coil to create RF plasma in the processing chamber. N flux attenuating portions are arranged in a spaced pattern adjacent the coil, wherein N is an integer greater than one.

Abstract translation: 基板处理系统包括处理室，该处理室包括介电窗口和用于在处理期间支撑基板的基座。 气体供应系统向处理室供应气体。 线圈被布置在与介电窗口相邻的处理室的外部。 射频（RF）源向线圈提供RF信号以在处理室中产生RF等离子体。 N个通量衰减部分以与线圈相邻的间隔布置的方式布置，其中N是大于1的整数。

公开(公告)号：US09396961B2

公开(公告)日：2016-07-19

申请号：US14612095

申请日：2015-02-02

Applicant: Lam Research Corporation

Inventor： Reza Arghavani ,  Shashank C. Deshmukh ,  Eric A. Hudson ,  Tom Kamp ,  Samantha Tan ,  Gerardo Adrian Delgadino

IPC: H01L21/311 ,  H01L21/67 ,  H01L21/263 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/321 ,  H01J37/32899 ,  H01L21/6719 ,  H01L21/67213 ,  H01L21/76897

Abstract: The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.

Abstract translation: 本文的实施例涉及用于蚀刻电介质材料中凹陷特征的方法和装置。 在各种实施例中，在两个蚀刻操作中形成凹陷特征。 第一蚀刻操作部分地蚀刻特征并且可以在配置成产生电容耦合等离子体的反应器中进行。 第一蚀刻操作可能在底层半导体材料由于穿过半导体材料顶部的电介质的离子穿透而经受显着的损坏之前结束。 第二蚀刻操作可以在配置成产生电感耦合等离子体的反应器中进行。 第一和第二蚀刻操作本身可以是多步循环过程。

公开(公告)号：US20150053347A1

公开(公告)日：2015-02-26

申请号：US14470544

申请日：2014-08-27

Applicant: Lam Research Corporation

Inventor： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile.

Abstract translation: 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据。 控制器还接收等离子体室中要处理的当前晶片的关键器件参数。 控制器基于至少一个先前处理的晶片的过程控制和温度数据以及当前晶片的关键器件参数来计算当前晶片的目标修整时间和目标温度分布。 当前的晶片在控制温度控制区域中的温度的同时进行修整操作，同时控制温度控制区域中的温度，从而基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US20140220709A1

公开(公告)日：2014-08-07

申请号：US13758266

申请日：2013-02-04

Applicant: LAM RESEARCH CORPORATION

Inventor： Yoshie Kimura ,  Tom Kamp ,  Eric Pape ,  Rohit DeshPande ,  Keith Gaff ,  Gowri Kamarthy

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/26 ,  H01J37/32724 ,  H01J37/32926 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67248 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

Abstract translation: 示例性实施例涉及通过控制等离子体处理系统中的温度调节时间来控制晶片的CD均匀性。 等离子体处理系统具有晶片支撑组件，其包括横跨卡盘的多个可独立控制的温度控制区域和控制每个温度控制区域的控制器。 控制器接收与先前在等离子体处理系统的等离子体室中处理的至少一个晶片相关联的过程控制和温度数据，以及在等离子体室中待处理的当前晶片的关键器件参数。 控制器基于过程控制和温度数据以及关键设备参数来计算当前晶片的目标修整时间和目标温度分布。 在目标修整时间期间修剪当前晶片，同时基于目标温度分布来控制每个器件管芯位置的温度。

公开(公告)号：US10714354B2

公开(公告)日：2020-07-14

申请号：US15447005

申请日：2017-03-01

Applicant: Lam Research Corporation

Inventor： Tom Kamp ,  Neema Rastgar ,  Michael Carl Drymon

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L21/67

Abstract: Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.

公开(公告)号：US20170178917A1

公开(公告)日：2017-06-22

申请号：US15447005

申请日：2017-03-01

Applicant: Lam Research Corporation

Inventor： Tom Kamp ,  Neema Rastgar ,  Michael Carl Drymon

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/308 ,  H01L21/311 ,  H01L21/67 ,  H01L21/02

CPC classification number: H01L21/3065 ,  H01J37/32091 ,  H01J37/321 ,  H01J37/3211 ,  H01J37/32449 ,  H01J2237/334 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/67069

Abstract: Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.

公开(公告)号：US20160181117A1

公开(公告)日：2016-06-23

申请号：US14612095

申请日：2015-02-02

Applicant: Lam Research Corporation

Inventor： Reza Arghavani ,  Shashank C. Deshmukh ,  Eric A. Hudson ,  Tom Kamp ,  Samantha Tan ,  Gerardo Adrian Delgadino

IPC: H01L21/311 ,  H01L21/67 ,  H01J37/32 ,  H01L21/263

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/321 ,  H01J37/32899 ,  H01L21/6719 ,  H01L21/67213 ,  H01L21/76897

Abstract: The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.

Abstract translation: 本文的实施例涉及用于蚀刻电介质材料中凹陷特征的方法和装置。 在各种实施例中，在两个蚀刻操作中形成凹陷特征。 第一蚀刻操作部分地蚀刻特征并且可以在配置成产生电容耦合等离子体的反应器中进行。 第一蚀刻操作可能在底层半导体材料由于穿过半导体材料顶部的电介质的离子穿透而经受显着的损坏之前结束。 第二蚀刻操作可以在配置成产生电感耦合等离子体的反应器中进行。 第一和第二蚀刻操作本身可以是多步循环过程。