公开(公告)号：US20140353661A1

公开(公告)日：2014-12-04

申请号：US14109339

申请日：2013-12-17

Applicant: LG DISPLAY CO., LTD.

Inventor： Hyun-Sik SEO ,  Jong-Woo KIM ,  Chung-Ho LEE

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L27/3279 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1244 ,  H01L29/45 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869

Abstract: A thin film transistor (TFT) array substrate is disclosed. The TFT array substrate includes a gate line, a first gate electrode branched from the gate line, a gate insulating film formed over the substrate, an active layer formed on the gate insulating film, a data line formed to comprise a plurality of metal layers including a first metal layer and a second metal layer formed of copper (Cu), a source electrode formed on the gate insulating film to comprise the remaining metal layer excluding the second metal layer among the plurality of the metal layers, and a drain electrode formed on the gate insulating film to comprise the remaining metal layer excluding the second metal layer among the plurality of the metal layers.

Abstract translation: 公开了薄膜晶体管（TFT）阵列基板。 TFT阵列基板包括栅极线，从栅极线分支的第一栅极电极，在基板上形成的栅极绝缘膜，形成在栅极绝缘膜上的有源层，形成为包括多个金属层的数据线，包括 由铜（Cu）形成的第一金属层和第二金属层，形成在所述栅极绝缘膜上以在所述多个金属层中包括除了所述第二金属层之外的剩余金属层的源电极和形成在 所述栅极绝缘膜在所述多个金属层中包括除了所述第二金属层之外的剩余金属层。

公开(公告)号：US20250089455A1

公开(公告)日：2025-03-13

申请号：US18750219

申请日：2024-06-21

Applicant: LG Display Co., Ltd.

Inventor： Jong-Woo KIM ,  Eung-Yong KIM

IPC: H10K59/121 ,  H10K59/80

Abstract: A display device includes first and second semiconductor layers on a substrate, the first and second semiconductor layers including a polycrystalline semiconductor material and an oxide semiconductor material, respectively. The device includes a first gate insulating layer on the first and second semiconductor layers. The device includes first and second gate electrodes on the first gate insulating layer, the first and second gate electrodes corresponding to the first and second semiconductor layers, respectively. The device includes a first interlayer insulating layer on the first gate electrode and the second gate electrode. The device includes first source and drain electrodes and second source and drain electrodes on the first interlayer insulating layer, the first source and drain electrodes connected to both end portions, respectively, of the first semiconductor layer, the second source and drain electrodes connected to both end portions, respectively, of the second semiconductor layer.