公开(公告)号：US20040145686A1

公开(公告)日：2004-07-29

申请号：US10753449

申请日：2004-01-09

Applicant: LG. PHILIPS LCD CO., LTD.

Inventor： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

IPC: G02F001/136 ,  G02F001/1333

CPC classification number: G02F1/133512 ,  G02F1/136286 ,  G02F2001/136295

Abstract: A liquid crystal display device and a method of fabricating the same are disclosed in the present invention. More specifically, the method includes the steps forming a gate line on the first substrate sequentially forming a first insulating layer, an amorphous silicon layer, and a metal layer on the first substrate, patterning the metal layer to form a data line, forming a second insulating layer on the data line, patterning the second insulating layer and the amorphous silicon layer to form a passivation layer and an active layer, respectively, forming a pixel electrode at a pixel region defined by the gate and data lines, assembling the first substrate and the second substrate having a black matrix thereon, wherein the black matrix vertically overlaps at least one boundary line defined by different exposures during step-and-repeat exposure processes; and forming a liquid crystal layer between the first and second substrates.

Abstract translation: 在本发明中公开了液晶显示装置及其制造方法。 更具体地，该方法包括以下步骤：在第一衬底上顺序地形成第一绝缘层，非晶硅层和金属层上的栅极线，在第一衬底上形成图案化金属层以形成数据线，形成第二 绝缘层，图案化第二绝缘层和非晶硅层，以形成钝化层和有源层，分别在由栅极和数据线限定的像素区域处形成像素电极，组装第一衬底和 所述第二衬底在其上具有黑色矩阵，其中所述黑色矩阵垂直重叠在步进和重复曝光过程期间由不同曝光限定的至少一个边界线; 以及在所述第一和第二基板之间形成液晶层。

公开(公告)号：US20040043545A1

公开(公告)日：2004-03-04

申请号：US10653283

申请日：2003-09-03

Applicant: LG. Philips LCD Co., Ltd.

Inventor： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

IPC: H01L031/036 ,  H01L029/04

CPC classification number: H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78669

Abstract: A TFT array substrate has a PAI pattern, and the PAI pattern has an over-etched portion of the pure amorphous silicon layer. This over-etched portion prevents a short between the pixel electrode and the pure amorphous silicon layer (i.e., the active layer). The over-etched portion also enables the aperture ratio to increase a gate line over a said substrate; a data line over the said substrate being perpendicular to the gate line; a passivation layer covering the data line, the passivation layer divided into a residual passivation layer and a etched passivation layer; a doped amorphous silicon layer formed under the data line and corresponding in size to the data line; a pure amorphous silicon layer formed under the doped amorphous silicon layer and having a over-etched portion in the peripheral portions, wherein the over-etched portion is over-etched from the edges of the residual passivation layer toward the inner side; an insulator layer under the pure amorphous silicon layer; a TFT formed near the crossing of the gate line and the data line; and a pixel electrode overlapping the data line and contacting the TFT.

Abstract translation: TFT阵列基板具有PAI图案，并且PAI图案具有纯非晶硅层的过蚀刻部分。 该过蚀刻部分防止像素电极和纯非晶硅层（即有源层）之间的短路。 过蚀刻部分还使孔径比增加了所述衬底上的栅极线; 所述衬底上的数据线垂直于所述栅极线; 覆盖数据线的钝化层，钝化层分为残留钝化层和蚀刻钝化层; 形成在数据线之下且与数据线大小对应的掺杂非晶硅层; 形成在掺杂非晶硅层下面并且在周边部分中具有过蚀刻部分的纯非晶硅层，其中过蚀刻部分从残余钝化层的边缘向内侧被过度蚀刻; 在纯非晶硅层下面的绝缘体层; 形成在栅极线和数据线的交叉点附近的TFT; 以及与数据线重叠并与TFT接触的像素电极。

公开(公告)号：US20040041959A1

公开(公告)日：2004-03-04

申请号：US10652311

申请日：2003-09-02

Applicant: LG. PHILIPS LCD CO., LTD.

Inventor： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

IPC: G02F001/136

CPC classification number: G02F1/136286 ,  G02F1/133345 ,  G02F1/136204 ,  G02F2201/50

Abstract: An array substrate for use in a liquid crystal display device is fabricated by the steps of forming a first metal layer on a substrate, patterning the first metal layer to form a gate line, a gate electrode, a gate pad, a first shorting bar, and a second shorting bar, forming a gate insulation layer, a pure amorphous silicon layer, a doped amorphous silicon layer and a second metal layer to cover the patterned first metal layer, patterning the second metal layer and the doped amorphous silicon layer to form first, second and third through-holes and first and second grooves to expose a portion of the pure amorphous silicon layer, the first and second grooves creating an isolated portions of the second metal layer, forming a passivation layer to cover the patterned second metal layer, forming a source electrode, a drain electrode, a data line, a data pad, an insulating segment, and first, second and third contact holes, and forming a pixel electrode, a first connector and a second connector of a transparent conductive material.

Abstract translation: 通过以下步骤制造用于液晶显示装置的阵列基板：在基板上形成第一金属层，图案化第一金属层以形成栅极线，栅电极，栅极焊盘，第一短路条， 以及第二短路棒，形成栅绝缘层，纯非晶硅层，掺杂非晶硅层和第二金属层以覆盖图案化的第一金属层，图案化第二金属层和掺杂的非晶硅层以形成第一 第二和第三通孔以及第一和第二凹槽以暴露纯非晶硅层的一部分，第一和第二凹槽产生第二金属层的隔离部分，形成钝化层以覆盖图案化的第二金属层， 形成源电极，漏电极，数据线，数据焊盘，绝缘段和第一，第二和第三接触孔，并形成像素电极，第一连接器和第二连接器 透明导电材料。