公开(公告)号：US20040266047A1

公开(公告)日：2004-12-30

申请号：US10878529

申请日：2004-06-29

发明人： Sang-Gab Kim ,  Sung-Chul Kang ,  Ho-Min Kang ,  In-Ho Song ,  Hee-Hwan Choe

IPC分类号： H01L031/036

CPC分类号： H01L27/1259 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262

摘要： A method of manufacturing a thin film array panel is provided, which includes: forming a gate line formed on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line and a drain electrode disposed at least on the ohmic contact layer; forming an oxide on the data line; etching the ohmic contact layer using the data line and the drain electrode as an etch mask; and forming a pixel electrode connected to the drain electrode.

摘要翻译： 提供一种制造薄膜阵列面板的方法，其包括：形成在基底上的栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在所述半导体层上形成欧姆接触层; 形成至少设置在所述欧姆接触层上的数据线和漏电极; 在数据线上形成氧化物; 使用数据线和漏电极作为蚀刻掩模蚀刻欧姆接触层; 以及形成连接到所述漏电极的像素电极。

公开(公告)号：US20040245552A1

公开(公告)日：2004-12-09

申请号：US10487526

申请日：2004-02-20

发明人： Ichiro Shiono ,  Kazuki Mizushima ,  Kenji Yamaguchi

IPC分类号： H01L029/04 ,  H01L031/036 ,  H01L021/8234 ,  H01L031/113 ,  C30B001/00

CPC分类号： H01L29/165 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66916

摘要： The present invention relates to a semiconductor substrate production method, field effect transistor production method, semiconductor substrate and field effect transistor which, together with having low penetrating dislocation density and low surface roughness, prevent worsening of surface and interface roughness during heat treatment of a device production process and so forth. A production method of a semiconductor substrate W, in which SiGe layers 2 and 3 are formed on an Si substrate 1, is comprised of a heat treatment step in which heat treatment is performed either during or after the formation of the SiGe layers by epitaxial growth, at a temperature that exceeds the temperature of the epitaxial growth, and a polishing step in which irregularities in the surface formed during the heat treatment are removed by polishing following formation of the SiGe layers.

摘要翻译： 半导体衬底制造方法，场效应晶体管制造方法，半导体衬底和场效应晶体管本发明涉及一种具有低穿透位错密度和低表面粗糙度的半导体衬底和场效应晶体管，防止器件热处理期间的表面变差和界面粗糙度 生产过程等等。 在Si衬底1上形成SiGe层2和3的半导体衬底W的制造方法包括热处理步骤，其中通过外延生长在SiGe层形成期间或之后进行热处理 ，在超过外延生长温度的温度下，以及抛光步骤，其中通过在形成SiGe层之后通过研磨去除在热处理期间形成的表面的凹凸。

公开(公告)号：US20040245527A1

公开(公告)日：2004-12-09

申请号：US10808333

申请日：2004-03-25

发明人： Kazuhito Tsukagoshi ,  Iwao Yagi ,  Yoshinobu Aoyagi

IPC分类号： H01L029/04 ,  H01L031/036

CPC分类号： H01L51/0508 ,  B82Y10/00 ,  H01L51/0021 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0545

摘要： Disclosed is a terminal for an organic material, which comprises a carbon nanotube to be in contact with an organic material having a 6-membered carbon ring, and a metal that is in contact with a part of the carbon nanotube. The carbon nanotube remarkably improves an electric conductivity between the organic material and the metal.

摘要翻译： 公开了一种有机材料的端子，其包括与具有6元碳环的有机材料接触的碳纳米管和与一部分碳纳米管接触的金属。 碳纳米管显着提高了有机材料与金属之间的电导率。

公开(公告)号：US20040238824A1

公开(公告)日：2004-12-02

申请号：US10865990

申请日：2004-06-14

发明人： Hye-Dong Kim ,  Jung Hyun Kwon

IPC分类号： H01L029/04 ,  H01L031/036

CPC分类号： H01L27/3246 ,  H01L27/3253 ,  H01L51/5253

摘要： An organic EL device includes a thin film transistor (TFT) array substrate including a first insulating substrate, a TFT formed on the first insulating substrate and a capacitor. It also includes an organic EL substrate including a second insulating substrate, and a transparent electrode, an organic EL layer and a metal electrode, which are sequentially stacked on the second insulating substrate. The TFT is coupled to the metal electrode.

摘要翻译： 有机EL器件包括：薄膜晶体管（TFT）阵列基板，包括第一绝缘基板，形成在第一绝缘基板上的TFT和电容器。 它还包括依次层叠在第二绝缘基板上的包括第二绝缘基板和透明电极，有机EL层和金属电极的有机EL基板。 TFT耦合到金属电极。

公开(公告)号：US20040238819A1

公开(公告)日：2004-12-02

申请号：US10826477

申请日：2004-04-16

申请人： The Regents of the University of California

发明人： Mariam N. Maghribi ,  Peter A. Krulevitch ,  Thomas S. Wilson ,  Julie K. Hamilton ,  Christina Park

IPC分类号： H01L029/04 ,  H01L031/036 ,  H01L023/48 ,  H05K001/00 ,  B32B031/00

CPC分类号： C08J5/18 ,  A61B5/04001 ,  A61B2562/02 ,  A61B2562/164 ,  A61N1/0452 ,  A61N1/0476 ,  A61N1/0492 ,  A61N1/05 ,  A61N1/0531 ,  A61N1/0534 ,  A61N1/0541 ,  A61N1/0543 ,  A61N1/0551 ,  A61N1/0553 ,  C08J2383/04 ,  H05K1/0283 ,  H05K1/118 ,  H05K2201/0133 ,  H05K2201/09263 ,  H05K2203/0271 ,  Y10T428/24917 ,  Y10T428/31663 ,  Y10T428/31707

摘要： A stretchable electronic apparatus and method of producing the apparatus. The apparatus has a central longitudinal axis and the apparatus is stretchable in a longitudinal direction generally aligned with the central longitudinal axis. The apparatus comprises a stretchable polymer body, and at least one circuit line operatively connected to the stretchable polymer body, the at least one circuit line extending in the longitudinal direction and having a longitudinal component that extends in the longitudinal direction and having an offset component that is at an angle to the longitudinal direction, the longitudinal component and the offset component allowing the apparatus to stretch in the longitudinal direction while maintaining the integrity of the at least one circuit line.

摘要翻译： 一种可拉伸电子设备及其制造方法。 该装置具有中心纵向轴线，并且该装置在大致与中心纵向轴线对准的纵向方向上是可拉伸的。 该装置包括可拉伸的聚合物主体，以及至少一个可操作地连接到可拉伸聚合物主体的电路线，所述至少一个电路线在纵向上延伸并且具有沿纵向方向延伸的纵向部件，并且具有偏移部件， 与纵向方向成一角度，纵向分量和偏移分量允许装置在纵向方向上拉伸，同时保持至少一条电路线的完整性。

公开(公告)号：US20040232421A1

公开(公告)日：2004-11-25

申请号：US10879587

申请日：2004-06-30

申请人： Hitachi, Ltd.

发明人： Kikuo Ono ,  Yoshiaki Nakayoshi ,  Ryutaro Oke ,  Toshiki Kaneko

IPC分类号： H01L029/04 ,  H01L031/036 ,  G02F001/1343 ,  G02F001/136

CPC分类号： G02F1/13458 ,  G02F1/134363 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136236 ,  G02F2001/13629 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1288

摘要： The present invention provides a novel photolithography processes using photoresist pattern having at least two areas which has different thickness from each other for a fabrication method for a liquid crystal display device having reversed staggered and channel-etched type thin film transistors, reduce a number of photolithography processes required for whole of the fabrication process of the liquid crystal display device, and improve brightness of the liquid crystal display device.

摘要翻译： 本发明提供了一种使用具有至少两个区域的光致抗蚀剂图案的新型光刻工艺，所述至少两个区域具有彼此不同的厚度，用于具有反向交错和沟道蚀刻型薄膜晶体管的液晶显示装置的制造方法，减少了许多光刻 液晶显示装置整体制造工序所需的工序，提高液晶显示装置的亮度。

公开(公告)号：US20040209407A1

公开(公告)日：2004-10-21

申请号：US10843453

申请日：2004-05-12

申请人： LG. Phillips LCD Co. , Ltd.

发明人： Gee-Sung Chae

IPC分类号： H01L021/84 ,  H01L031/036

CPC分类号： H01L27/124 ,  G02F1/136286 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66765

摘要： The present invention discloses a TFT array substrate that is fabricated using a four-mask process and a method of manufacturing that TFT array substrate. The gate line and gate electrode of the array substrate is surrounded by the metallic oxide after finishing a first mask process using thermal treatment. As a result, the gate line and gate electrode are not eroded and damaged by the etchant and stripper during a fourth mask process. Further, buffering layer can optionally be formed between the substrate and the gate line and gate electrode. Thus, silicon ions and oxygen ions included in the substrate are not diffused into the gate line and electrode. Accordingly, the line defect such as a line open of the gate line and gate electrode is prevented, thereby preventing inferior goods while increasing the manufacturing yield.

公开(公告)号：US20040183073A1

公开(公告)日：2004-09-23

申请号：US10767525

申请日：2004-01-29

发明人： Shuo Gu

IPC分类号： H01L029/76 ,  H01L031/036 ,  H01L031/112 ,  C30B001/00

CPC分类号： C30B29/06 ,  C30B25/02 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02667 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/6675 ,  H01L29/78672

摘要： A method to enhance grain size in polysilicon films while avoiding formation of hemispherical grains (HSG) is disclosed. The method begins by depositing a first amorphous silicon film, then depositing silicon nuclei, which will act as nucleation sites, on the amorphous film. After deposition of silicon nuclei, crystallization, and specifically HSG, is prevented by lowering temperature and/or raising pressure. Next a second amorphous silicon layer is deposited over the first layer and the nuclei. Finally an anneal is performed to induce crystallization from the embedded nuclei. Thus grains are formed from the silicon bulk, rather than from the surface, HSG is avoided, and a smooth polysilicon film with enhanced grain size is produced.

公开(公告)号：US20040174189A1

公开(公告)日：2004-09-09

申请号：US10699797

申请日：2003-11-04

申请人： Semiconductor Energy Laboratory Co. Ltd., a Japan corporation

发明人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

IPC分类号： H03K019/096 ,  H03K017/687 ,  H01L031/036 ,  H03K017/16

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0254 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08 ,  G11C19/00 ,  G11C19/28 ,  H01L2924/0002 ,  H03K19/01735 ,  H03K19/096 ,  H01L2924/00

摘要： A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDDnullV thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDDnullV thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.

摘要翻译： 提供一种电路，其由一种导电类型的TFT构成，并且能够输出正常振幅的信号。 当输入时钟信号CK1变为高电平时，TFT（101,103）中的每一个导通以将信号输出部分（Out）处的电位置为低电平。 然后将脉冲输入到信号输入部（In）并变为高电平。 TFT（102）的栅极电位增加到（VDD-V thN），栅极浮起来。 TFT（102）因此被导通。 然后，CK1变为低电平，并且每个TFT（101,103）被关断。 同时，CK3变为高电平，信号输出部分的电位增加。 同时，通过电容器（104）的功能，TFT（102）的栅极处的电位增加到等于或高于（VDD + V thN）的电平，使得出现在信号输出部分（Out ）变为等于VDD。 当SP变低时 CK3变低 并且CK1变为高电平时，信号输出部（Out）的电位再次变为低电平。

公开(公告)号：US20040129943A1

公开(公告)日：2004-07-08

申请号：US10705913

申请日：2003-11-13

发明人： Soon Sung Yoo ,  Youn Gyoung Chang ,  Heung Lyul Cho

IPC分类号： G02F001/136 ,  H01L021/84 ,  H01L031/036

CPC分类号： H01L27/124 ,  G02F1/13458 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1288 ,  Y10S438/942

摘要： A thin film transistor array substrate has a gate electrode of the thin film transistor, a gate line connected to the gate electrode, and a gate pad connected to the gate line; a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, a data pad connected to the data line, a storage electrode formed and superimposed with the gate line; a semiconductor pattern formed in low part of the substrate; a transparent electrode pattern including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode covering the data pad; and a protection pattern and a gate insulation pattern stacked in a region other than the region where the transparent electrode pattern is formed.

摘要翻译： 薄膜晶体管阵列基板具有薄膜晶体管的栅电极，连接到栅电极的栅极线和连接到栅极线的栅极焊盘; 源极/漏极图案，包括薄膜晶体管的源电极和漏电极，连接到源电极的数据线，连接到数据线的数据焊盘，形成并与栅极线重叠的存储电极; 形成在基板的低部分的半导体图案; 包括连接到漏电极和存储电极的像素电极的透明电极图案，覆盖栅极焊盘的栅极焊盘保护电极和覆盖数据焊盘的数据焊盘保护电极; 以及层叠在除了形成透明电极图案的区域以外的区域中的保护图案和栅极绝缘图案。