公开(公告)号：US20180202966A1

公开(公告)日：2018-07-19

申请号：US15789850

申请日：2017-10-20

Applicant: LIFE TECHNOLOGIES CORPORATION

Inventor： Keith FIFE

IPC: G01N27/414 ,  G01N27/30

CPC classification number: G01N27/414 ,  G01N27/302 ,  G01N27/4145 ,  G01N27/4148

Abstract: An ion-sensitive circuit can include a charge accumulation device, to accumulate a plurality of charge packets as a function of an ion concentration of a fluid, and at least one control and readout transistor, to generate an output signal as a function of the accumulated plurality of charge packets, the output signal representing the ion concentration of the solution. The charge accumulation device can include a first charge control electrode above a first electrode semiconductor region, an electrically floating gate structure above a gate semiconductor region and below an ion-sensitive passivation surface, a second charge control electrode above a second electrode semiconductor region, and a drain diffusion region. The first control electrode can control entry of charge into a gate semiconductor region in response to a first control signal. The ion-sensitive passivation surface can be configured to receive the fluid. The second charge control electrode can control transmission of the plurality of charge packets out of the gate semiconductor region and into the drain diffusion region in response to a second control signal. The drain diffusion region can receive the plurality of charge packets from the gate semiconductor region via the second electrode semiconductor region.

公开(公告)号：US20190339229A1

公开(公告)日：2019-11-07

申请号：US16510743

申请日：2019-07-12

Applicant: Life Technologies Corporation

Inventor： Keith FIFE

IPC: G01N27/414

Abstract: A semiconductor device, comprising a first field effect transistor (FET) connected in series to a second FET, and a third FET connected in series to the first FET and the second FET. The semiconductor device further includes bias circuitry coupled to the first FET and the second FET, and an output conductor coupled to a terminal of the second FET, wherein the output conductor obtains an output signal from the second FET that is independent of the first FET.

公开(公告)号：US20190033363A1

公开(公告)日：2019-01-31

申请号：US15979439

申请日：2018-05-14

Applicant: LIFE TECHNOLOGIES CORPORATION

Inventor： Jarie BOLANDER ,  Keith FIFE ,  Mark MILGREW

IPC: G01R31/26 ,  G01R31/28 ,  G01N27/414

Abstract: The invention provides testing of a chemically-sensitive transistor device, such as an ISFET device, without exposing the device to liquids. In one embodiment, the invention performs a first test to calculate a resistance of the transistor. Based on the resistance, the invention performs a second test to transition the testing transistor among a plurality of modes. Based on corresponding measurements, a floating gate voltage is then calculated with little or no circuitry overhead. In another embodiment, the parasitic capacitance of at least either the source or drain is used to bias the floating gate of an ISFET. A driving voltage and biasing current are applied to exploit the parasitic capacitance to test the functionality of the transistor.