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1.发明申请公开(公告)号：US20210217862A1
公开(公告)日：2021-07-15
申请号：US17157350
申请日：2021-01-25
IPC分类号： H01L29/423 , H01L21/28 , H01L29/792 , H01L29/51 , H01L29/66 , B82Y10/00 , H01L27/11526 , G11C16/04 , H01L27/11563 , H01L29/49 , H01L21/02 , H01L29/06 , H01L27/11568 , H01L27/11573 , H01L27/11575
摘要： An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
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2.发明公开公开(公告)号：US20240332385A1
公开(公告)日：2024-10-03
申请号：US18739179
申请日：2024-06-10
IPC分类号： H01L29/423 , B82Y10/00 , G11C16/04 , H01L21/02 , H01L21/28 , H01L29/06 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/792 , H10B41/40 , H10B43/00 , H10B43/30 , H10B43/40 , H10B43/50
CPC分类号： H01L29/4234 , B82Y10/00 , G11C16/0466 , H01L21/0214 , H01L21/02532 , H01L21/02595 , H01L29/0649 , H01L29/0676 , H01L29/40117 , H01L29/42344 , H01L29/4916 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66795 , H01L29/66833 , H01L29/792 , H01L29/7926 , H10B41/40 , H10B43/00 , H10B43/30 , H10B43/40 , H10B43/50
摘要： An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
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3.发明授权公开(公告)号：US12009401B2
公开(公告)日：2024-06-11
申请号：US17952796
申请日：2022-09-26
IPC分类号： H01L27/11526 , B82Y10/00 , G11C16/04 , H01L21/02 , H01L21/28 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/792 , H10B41/40 , H10B43/00 , H10B43/30 , H10B43/40 , H10B43/50
CPC分类号： H01L29/4234 , B82Y10/00 , G11C16/0466 , H01L21/0214 , H01L21/02532 , H01L21/02595 , H01L29/0649 , H01L29/0676 , H01L29/40117 , H01L29/42344 , H01L29/4916 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66795 , H01L29/66833 , H01L29/792 , H01L29/7926 , H10B41/40 , H10B43/00 , H10B43/30 , H10B43/40 , H10B43/50
摘要： An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
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4.发明授权公开(公告)号：US10903325B2
公开(公告)日：2021-01-26
申请号：US16429464
申请日：2019-06-03
IPC分类号： H01L27/00 , H01L29/00 , G11C16/04 , H01L29/423 , H01L21/28 , H01L29/792 , H01L29/51 , H01L29/66 , B82Y10/00 , H01L27/11526 , H01L27/11563 , H01L29/49 , H01L21/02 , H01L29/06 , H01L27/11568 , H01L27/11573 , H01L27/11575
摘要： An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
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5.发明申请公开(公告)号：US20200152752A1
公开(公告)日：2020-05-14
申请号：US16600768
申请日：2019-10-14
IPC分类号： H01L29/423 , H01L29/51 , H01L29/06 , H01L27/11575 , H01L27/11573 , H01L27/11568 , H01L29/66 , H01L21/02 , H01L29/49 , H01L27/11563 , G11C16/04 , H01L27/11526 , B82Y10/00 , H01L29/792 , H01L21/28
摘要： Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed.
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6.发明申请公开(公告)号：US20220005929A1
公开(公告)日：2022-01-06
申请号：US17366934
申请日：2021-07-02
IPC分类号： H01L29/423 , H01L21/28 , H01L29/792 , H01L29/51 , H01L29/66 , B82Y10/00 , H01L27/11526 , G11C16/04 , H01L27/11563 , H01L29/49 , H01L21/02 , H01L29/06 , H01L27/11568 , H01L27/11573 , H01L27/11575
摘要： Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed.
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公开(公告)号：US11056565B2
公开(公告)日：2021-07-06
申请号：US16600768
申请日：2019-10-14
IPC分类号： H01L21/00 , H01L27/00 , H01L29/00 , G11C16/04 , H01L29/423 , H01L21/28 , H01L29/792 , H01L29/51 , H01L29/66 , B82Y10/00 , H01L27/11526 , H01L27/11563 , H01L29/49 , H01L21/02 , H01L29/06 , H01L27/11568 , H01L27/11573 , H01L27/11575
摘要： Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed.
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8.发明申请公开(公告)号：US20200013863A1
公开(公告)日：2020-01-09
申请号：US16429464
申请日：2019-06-03
IPC分类号： H01L29/423 , H01L29/51 , H01L29/06 , H01L27/11575 , H01L27/11573 , H01L27/11568 , H01L29/66 , H01L21/02 , H01L29/49 , H01L27/11563 , G11C16/04 , H01L27/11526 , B82Y10/00 , H01L29/792 , H01L21/28
摘要： An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
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9.发明授权公开(公告)号：US10411103B2
公开(公告)日：2019-09-10
申请号：US15376282
申请日：2016-12-12
IPC分类号： H01L27/00 , H01L29/00 , H01L29/423 , H01L29/792 , H01L29/51 , H01L29/66 , B82Y10/00 , H01L21/28 , H01L27/11526 , G11C16/04 , H01L27/11563 , H01L29/49 , H01L21/02 , H01L29/06 , H01L27/11568 , H01L27/11573 , H01L27/11575
摘要： Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed.
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10.发明申请公开(公告)号：US20230023852A1
公开(公告)日：2023-01-26
申请号：US17952796
申请日：2022-09-26
IPC分类号： H01L29/423 , H01L21/28 , H01L29/792 , H01L29/51 , H01L29/66 , B82Y10/00 , H01L27/11526 , G11C16/04 , H01L27/11563 , H01L29/49 , H01L21/02 , H01L29/06 , H01L27/11568 , H01L27/11573 , H01L27/11575
摘要： An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
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