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公开(公告)号：US20140122959A1
公开(公告)日：2014-05-01
申请号：US13664490
申请日：2012-10-31
Applicant: LSI CORPORATION
IPC: H03M13/13
CPC classification number: H03M13/1111 , H03M13/116
Abstract: A method for determining update candidates in a low-density parity-check decoding process includes dividing the quasi-cyclic columns into groups and identifying an update candidate in each group. One or more of the identified update candidates are then updated.
Abstract translation: 一种用于在低密度奇偶校验解码过程中确定更新候选的方法，包括将准循环列分成组并识别每组中的更新候选。 然后更新所识别的更新候选中的一个或多个。
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公开(公告)号：US08797666B2
公开(公告)日：2014-08-05
申请号：US13650562
申请日：2012-10-12
Applicant: LSI Corporation
Inventor： Haitao Xia , Lei Chen
IPC: G11B20/10
CPC classification number: H04L25/03171 , H04L25/03197 , H04L25/03299 , H04L2025/03503
Abstract: An adaptive detector, such as a maximum a posteriori (MAP) detector for a read channel, is disclosed. In one or more embodiments, a data processing apparatus, such as a read channel digital front end, includes an equalizer configured to equalize X sample data to yield equalized Y sample data. A noise predictive filter configured to receive the equalized Y sample data yielded by the equalizer is operable to filter noise in the equalized Y sample data. A detector is configured to perform iterative data detection on the filtered equalized Y sample data. The detector is operable to program a branch metric, a variance, and a scaling factor for equalizer adaptation during a global iteration of the detector.
Abstract translation: 公开了一种自适应检测器，例如用于读通道的最大后验（MAP）检测器。 在一个或多个实施例中，诸如读通道数字前端的数据处理设备包括均衡器，其被配置为均衡X采样数据以产生均衡的Y采样数据。 被配置为接收由均衡器产生的均衡的Y采样数据的噪声预测滤波器可操作以滤除均衡的Y采样数据中的噪声。 检测器被配置为对经过滤的均衡Y样本数据执行迭代数据检测。 检测器可操作以在检测器的全局迭代期间对用于均衡器适配的分支度量，方差和缩放因子进行编程。
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公开(公告)号：US09281841B2
公开(公告)日：2016-03-08
申请号：US13664490
申请日：2012-10-31
Applicant: LSI Corporation
CPC classification number: H03M13/1111 , H03M13/116
Abstract: A method for determining update candidates in a low-density parity-check decoding process includes dividing the quasi-cyclic columns into groups and identifying an update candidate in each group. One or more of the identified update candidates are then updated. In the first half of iterative process, the higher quality candidate is updated. In the second half of the iterative process, the lower quality candidate is updated.
Abstract translation: 一种用于在低密度奇偶校验解码过程中确定更新候选的方法，包括将准循环列分成组并识别每组中的更新候选。 然后更新所识别的更新候选中的一个或多个。 在迭代过程的前半部分，更高质量的候选人被更新。 在迭代过程的后半部分，更低质量的候选者被更新。
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4.发明授权Data sequence detection in band-limited channels using two stream detector architecture 有权使用两个流检测器架构的带限通道中的数据序列检测公开(公告)号：US08810950B1
公开(公告)日：2014-08-19
申请号：US13842259
申请日：2013-03-15
Applicant: LSI Corporation
Inventor： Madhusudan Kalluri , Sathiyanarayanan Sampath Kumar , Jianqing Chen , Lei Chen , Johnson Yen , Sancar K. Olcay
CPC classification number: G11B20/10046
Abstract: A method for data sequence detection includes generating a first sample stream, equalizing the first sample stream to generate a first equalized sample stream, and buffering the first equalized sample stream. The first sample stream is interpolated to generate a second sample stream. The second sample stream is equalized to generate a second equalized sample stream. In a first processing path, the samples of the buffered first equalized sample stream are filtered using a first noise predictive filter bank to generate a first set of noise sample streams. In a second parallel processing path, the samples of the buffered first equalized sample stream are interpolated using a second interpolation filter to generate an interpolated sample stream and the interpolated sample stream is filtered to generate a second set of noise sample streams. The first equalized sample stream and the second equalized sample stream are processed to generate adapted filter coefficients for the second interpolation filter. The first and second set of noise sample streams are diversity combined to generate a set of combined noise sample streams. A data sequence is detected using the set of combined noise sample streams.
Abstract translation: 一种用于数据序列检测的方法包括生成第一样本流，使第一样本流均衡以产生第一均衡样本流，以及缓冲第一均衡样本流。 内插第一采样流以产生第二采样流。 第二样本流被均衡以产生第二均衡样本流。 在第一处理路径中，使用第一噪声预测滤波器组对缓冲的第一均衡采样流的采样进行滤波，以产生第一组噪声采样流。 在第二并行处理路径中，使用第二内插滤波器对缓冲的第一均衡采样流的样本进行内插，以生成内插采样流，并且内插采样流被滤波以产生第二组噪声采样流。 处理第一均衡采样流和第二均衡采样流，以生成适用于第二内插滤波器的滤波器系数。 第一和第二组噪声采样流被分集组合以产生一组组合的噪声采样流。 使用组合的噪声采样流来检测数据序列。
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5.发明申请LEH Memory Module Architecture Design in the Multi-Level LDPC Coded Iterative System 有权LEH存储器模块体系结构在多级LDPC编码迭代系统中的设计公开(公告)号：US20140122971A1
公开(公告)日：2014-05-01
申请号：US13663006
申请日：2012-10-29
Applicant: LSI CORPORATION
Inventor： Zongwang Li , Lei Chen , Shaohua Yang , Johnson Yen
CPC classification number: H03M13/6505 , H03M13/1111 , H03M13/1137 , H03M13/27 , H03M13/6331
Abstract: A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue.
Abstract translation: LDPC解码系统中的存储器包括组织成乒乓存储器的数据库。 乒乓存储器连接到交织器和解交织器。 交织器交织L值; 然后将交错的L值存储在乒乓存储器中。 LDPC解码器从乒乓存储器检索L值并将E值返回给乒乓存储器。 解交织器对E值进行解交织，并将数据发送到LE队列和HD队列。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20140105266A1
公开(公告)日：2014-04-17
申请号：US13650562
申请日：2012-10-12
Applicant: LSI CORPORATION
Inventor： Haitao Xia , Lei Chen
IPC: H04L27/01
CPC classification number: H04L25/03171 , H04L25/03197 , H04L25/03299 , H04L2025/03503
Abstract: An adaptive detector, such as a maximum a posteriori (MAP) detector for a read channel, is disclosed. In one or more embodiments, a data processing apparatus, such as a read channel digital front end, includes an equalizer configured to equalize X sample data to yield equalized Y sample data. A noise predictive filter configured to receive the equalized Y sample data yielded by the equalizer is operable to filter noise in the equalized Y sample data. A detector is configured to perform iterative data detection on the filtered equalized Y sample data. The detector is operable to program a branch metric, a variance, and a scaling factor for equalizer adaptation during a global iteration of the detector.
Abstract translation: 公开了一种自适应检测器，例如用于读通道的最大后验（MAP）检测器。 在一个或多个实施例中，诸如读通道数字前端的数据处理设备包括均衡器，其被配置为均衡X采样数据以产生均衡的Y采样数据。 被配置为接收由均衡器产生的均衡的Y采样数据的噪声预测滤波器可操作以滤除均衡的Y采样数据中的噪声。 检测器被配置为对经过滤的均衡Y样本数据执行迭代数据检测。 检测器可操作以在检测器的全局迭代期间对用于均衡器适配的分支度量，方差和缩放因子进行编程。
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公开(公告)号：US20140095954A1
公开(公告)日：2014-04-03
申请号：US13629726
申请日：2012-09-28
Applicant: LSI CORPORATION
Inventor： Chung-Li Wang , Lei Chen , Fan Zhang , Shaohua Yang , Qi Qi
IPC: H03M13/05
CPC classification number: H03M13/1108 , H03M13/3738
Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.
Abstract translation: LDPC解码器包括用于不满足检查的LDPC码字中的可疑比特的目标符号翻转的处理器。 检查索引和可变索引的所有组合被编译并且相关联到目标符号翻转候选的池中，并且与符号索引一起返回到使用这样的符号索引来识别符号以便打破陷阱集合的过程。
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8.发明授权LEH memory module architecture design in the multi-level LDPC coded iterative system 有权LEH存储器模块架构设计在多级LDPC编码迭代系统中公开(公告)号：US09219504B2
公开(公告)日：2015-12-22
申请号：US13663006
申请日：2012-10-29
Applicant: LSI Corporation
Inventor： Zongwang Li , Lei Chen , Shaohua Yang , Johnson Yen
CPC classification number: H03M13/6505 , H03M13/1111 , H03M13/1137 , H03M13/27 , H03M13/6331
Abstract: A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue.
Abstract translation: LDPC解码系统中的存储器包括组织成乒乓存储器的数据库。 乒乓存储器连接到交织器和解交织器。 交织器交织L值; 然后将交错的L值存储在乒乓存储器中。 LDPC解码器从乒乓存储器检索L值并将E值返回给乒乓存储器。 解交织器对E值进行解交织，并将数据发送到LE队列和HD队列。
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公开(公告)号：US09189379B2
公开(公告)日：2015-11-17
申请号：US13760447
申请日：2013-02-06
Applicant: LSI Corporation
Inventor： Herjen Wang , Ngok Ying Chu , Johnson Yen , Lei Chen
CPC classification number: G06F12/00 , G11C29/022 , G11C29/028
Abstract: The disclosure is directed to a system for managing data samples utilizing a time division multiplexing controller to allocate time slots for accessing a sample memory according to one or more modes of operation. The time division multiplexing controller is configured to allocate slots for concurrent access by a sample controller, a plurality of detectors, and a noise predictive calibrator when a normal mode is enabled. The time division multiplexing controller is further configured to allocate slots excluding at least one of the sample controller, the plurality of detectors, and the noise predictive calibrator from accessing the sample memory when a retry mode is enabled. In some embodiments, the time division multiplexing controller is further configured to allocate time slots for one or more clients other than the sample controller, the plurality of detectors, and the noise predictive calibrator.
Abstract translation: 本公开涉及一种利用时分复用控制器来管理数据样本的系统，以分配用于根据一种或多种操作模式访问采样存储器的时隙。 时分复用控制器被配置为当正常模式被使能时，由采样控制器，多个检测器和噪声预测校准器分配用于并行访问的时隙。 时分复用控制器还被配置为当重试模式被使能时，分配除了样本控制器，多个检测器和噪声预测校准器中的至少一个的时隙以访问采样存储器。 在一些实施例中，时分复用控制器还被配置为为除了采样控制器，多个检测器和噪声预测校准器之外的一个或多个客户端分配时隙。
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10.发明授权Hardware architecture and implementation of low power layered multi-level LDPC decoder 有权低功耗分层多级LDPC解码器的硬件架构与实现公开(公告)号：US09037938B2
公开(公告)日：2015-05-19
申请号：US13664071
申请日：2012-10-30
Applicant: LSI Corporation
Inventor： Lei Chen , Johnson Yen , Zongwang Li , Chung-Li Wang
CPC classification number: H03M13/29 , G11B20/1833 , H03M13/1122 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1171 , H03M13/27 , H03M13/2957 , H03M13/658 , H03M13/6591
Abstract: A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed.
Abstract translation: 分层LDPC解码器根据入口大小对消息条目的子集进行排序和选择进行处理。 子集中每个消息条目的MIN1和MIN2值被截断，并且基于消息条目的子集是否包含与被处理的层相关联的变量节点，截断值或非截断值与符号向量组合。
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