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18 条记录 (耗时 0.016 秒)

    Video optimized LCD response time compensation
    1.
    发明授权
    Video optimized LCD response time compensation 有权
    视频优化LCD响应时间补偿

    公开(公告)号：US08049741B2

    公开(公告)日：2011-11-01

    申请号：US11329927

    申请日：2006-01-11

    申请人： Lawrence E. Knepper ,  Randall E. Juenger ,  Thomas P. Lanzoni

    发明人： Lawrence E. Knepper ,  Randall E. Juenger ,  Thomas P. Lanzoni

    IPC分类号： G09G5/00

    CPC分类号： G09G3/3611 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2320/106 ,  G09G2340/16

    摘要： An improved system and method for selectively applying LCD Response Time Compensation (LRTC) to areas of an LCD panel containing video motion. Motion vectors contained within macroblocks in a compressed video stream are utilized to qualify whether individual pixels in a video frame are a candidate for LRTC. In various embodiments of the invention, computationally expensive LRTC can be selectively applied, pixel-by-pixel, which can result in portable information system power savings by reducing the number of computational cycles and the amount of graphics controller power overhead.

    摘要翻译： 一种用于选择性地将LCD响应时间补偿（LRTC）应用于包含视频运动的LCD面板的区域的改进的系统和方法。 使用包含在压缩视频流中的宏块内的运动矢量来限定视频帧中的各个像素是LRTC的候选。 在本发明的各种实施例中，可以逐个像素地选择性地应用计算上昂贵的LRTC，这可以通过减少计算周期的数量和图形控制器功率开销的量来导致便携式信息系统的功率节省。

    Secondary graphics processor control system
    2.
    发明授权
    Secondary graphics processor control system 有权
    二级图形处理器控制系统

    公开(公告)号：US09110664B2

    公开(公告)日：2015-08-18

    申请号：US13452181

    申请日：2012-04-20

    申请人： Thomas P. Lanzoni ,  Ajay Kwatra ,  Randall E. Juenger

    发明人： Thomas P. Lanzoni ,  Ajay Kwatra ,  Randall E. Juenger

    IPC分类号： G06F15/16 ,  G06F1/32 ,  G06F9/50

    CPC分类号： G06F1/3218 ,  G06F1/3212 ,  G06F1/3265 ,  G06F9/5094 ,  Y02D10/153 ,  Y02D10/174 ,  Y02D10/22

    摘要： A secondary graphics processor control system includes a secondary graphics processor. A controller is coupled to the secondary graphics processor. The controller detects the start of an application that is associated with a secondary graphics processor and then determines a power capability of a battery. The controller then either prevents enablement of the secondary graphics processor if the power capability is below a predetermined threshold such that only a primary graphics processor processes graphics for the application, or allows enablement of the secondary graphics processor if the power capability is above the predetermined threshold such that the secondary graphics processor processing graphics for the application. The primary graphics processor may be an integrated graphics processing unit (iGPU) provided by a system processor that is mounted to a board, and the secondary graphics processor may be a discrete graphics processing unit (dGPU) that is coupled to the board.

    摘要翻译： 辅助图形处理器控制系统包括辅助图形处理器。 控制器耦合到辅助图形处理器。 控制器检测与二级图形处理器相关联的应用的开始，然后确定电池的功率能力。 然后，如果功率能力低于预定阈值，则控制器可以防止辅助图形处理器的启用，使得只有主图形处理器处理应用的图形，或者如果功率能力高于预定阈值则允许辅助图形处理器的启用 使二级图形处理器处理图形的应用。 主图形处理器可以是由安装到板的系统处理器提供的集成图形处理单元（iGPU），并且辅助图形处理器可以是耦合到板的分立图形处理单元（dGPU）。

    SECONDARY GRAPHICS PROCESSOR CONTROL SYSTEM
    3.
    发明申请
    SECONDARY GRAPHICS PROCESSOR CONTROL SYSTEM 有权
    二次图形处理器控制系统

    公开(公告)号：US20130278613A1

    公开(公告)日：2013-10-24

    申请号：US13452181

    申请日：2012-04-20

    申请人： Thomas P. Lanzoni ,  Ajay Kwatra ,  Randall E. Juenger

    发明人： Thomas P. Lanzoni ,  Ajay Kwatra ,  Randall E. Juenger

    IPC分类号： G06F15/16 ,  G06F13/14

    CPC分类号： G06F1/3218 ,  G06F1/3212 ,  G06F1/3265 ,  G06F9/5094 ,  Y02D10/153 ,  Y02D10/174 ,  Y02D10/22

    摘要： A secondary graphics processor control system includes a secondary graphics processor. A controller is coupled to the secondary graphics processor. The controller detects the start of an application that is associated with a secondary graphics processor and then determines a power capability of a battery. The controller then either prevents enablement of the secondary graphics processor if the power capability is below a predetermined threshold such that only a primary graphics processor processes graphics for the application, or allows enablement of the secondary graphics processor if the power capability is above the predetermined threshold such that the secondary graphics processor processing graphics for the application. The primary graphics processor may be an integrated graphics processing unit (iGPU) provided by a system processor that is mounted to a board, and the secondary graphics processor may be a discrete graphics processing unit (dGPU) that is coupled to the board.

    摘要翻译： 辅助图形处理器控制系统包括辅助图形处理器。 控制器耦合到辅助图形处理器。 控制器检测与二级图形处理器相关联的应用的开始，然后确定电池的功率能力。 然后，如果功率能力低于预定阈值，则控制器可防止辅助图形处理器的启用，使得只有主图形处理器处理用于应用的图形，或者如果功率能力高于预定阈值则允许辅助图形处理器的启用 使二级图形处理器处理图形的应用。 主图形处理器可以是由安装到板的系统处理器提供的集成图形处理单元（iGPU），并且辅助图形处理器可以是耦合到板的分立图形处理单元（dGPU）。

    System and method for DVI native and docking support
    5.
    发明授权
    System and method for DVI native and docking support 有权
    DVI本机和对接支持的系统和方法

    公开(公告)号：US07624218B2

    公开(公告)日：2009-11-24

    申请号：US10689253

    申请日：2003-10-20

    申请人： Randall E. Juenger

    发明人： Randall E. Juenger

    IPC分类号： G06F13/00

    CPC分类号： G09G5/006

    摘要： DVI native and docking station support for a portable information handling system provides output of display information from a either DVI connector at the portable information handling system housing or from a DVI connector at the portable information handling system docking station. A DVO signal outputs from a graphics component to a multiplexer that selectively provides the DVO signal to a TMDS transmitter associated with a housing DVI connector or to a TMDS transmitter associated with a docking station to information handling system connector and docking station DVI connector. Selection of the housing TMDS transmitter to receive the DVO signal is made if the information handling system is not coupled to the docking station, and selection of the docking station TMDS transmitter to receive the DVO signal is made if the information handling system is coupled to the docking station at the docking station connector.

    摘要翻译： 便携式信息处理系统的DVI本地和对接站支持从便携式信息处理系统外壳上的DVI连接器或便携式信息处理系统对接站处的DVI连接器输出显示信息。 DVO信号从图形组件输出到多路复用器，其选择性地将DVO信号提供给与壳体DVI连接器相关联的TMDS发射器或与对接站相关联的TMDS发射器到信息处理系统连接器和对接站DVI连接器。 如果信息处理系统没有耦合到对接站，则选择外壳TMDS发送器来接收DVO信号，并且如果信息处理系统耦合到对接站，则选择对接站TMDS发送器来接收DVO信号 对接站在对接站连接器。

    Dynamic switching of parallel termination for power management with DDR memory
    6.
    发明授权
    Dynamic switching of parallel termination for power management with DDR memory 有权
    使用DDR内存进行电源管理的并行终端的动态切换

    公开(公告)号：US06894691B2

    公开(公告)日：2005-05-17

    申请号：US10136067

    申请日：2002-05-01

    申请人： Randall E. Juenger

    发明人： Randall E. Juenger

    IPC分类号： G06F3/14 ,  G09G5/39 ,  H03K17/16

    CPC分类号： G09G5/39 ,  G06F3/14 ,  G09G2330/021 ,  G09G2360/12

    摘要： A system and method for managing power consumption of an information handling system dynamically switches between high and low clock speed data transfers with double data rate (DDR) memory. The selection of a high clock speed dynamically switches the DDR memory to connect to a parallel termination for more rapid data transfers with increased power consumption. The selection of a low clock speed dynamically switches the DDR memory to disconnect the parallel termination for slower data transfers with reduced power consumption. In one embodiment, portable computer graphics DDR memory reduces power consumption by selecting low clock speed transfers without parallel termination when operating on internal power. The portable computer graphics DDR memory provides improved display resolution by selecting high clock speed transfers with parallel termination when operating on external power or when displaying information from high resolution applications.

    摘要翻译： 用于管理信息处理系统的功耗的系统和方法在具有双倍数据速率（DDR）存储器的高和低时钟速度数据传输之间动态地切换。 高速时钟速度的选择动态地切换DDR存储器以连接到并行终端，从而更快速地进行数据传输，并增加功耗。 选择低时钟速度可以动态地切换DDR存储器，以便以较低的功耗消除并行终端，从而实现较慢的数据传输。 在一个实施例中，便携式计算机图形DDR存储器通过选择低时钟速度传输来减少功耗，而不需要在内部电源运行时并行终止。 便携式计算机图形DDR存储器通过在外部电源运行时或当显示来自高分辨率应用的信息时选择具有并行终端的高速时钟速度传输来提供改进的显示分辨率

    System and Method for Managing Multiple Independent Graphics Sources in an Information Handling System
    8.
    发明申请
    System and Method for Managing Multiple Independent Graphics Sources in an Information Handling System 有权
    在信息处理系统中管理多个独立图形源的系统和方法

    公开(公告)号：US20110052142A1

    公开(公告)日：2011-03-03

    申请号：US12549954

    申请日：2009-08-28

    申请人： Andrew T. Sultenfuss ,  Randall E. Juenger

    发明人： Andrew T. Sultenfuss ,  Randall E. Juenger

    IPC分类号： H04N7/01 ,  H04N5/765

    CPC分类号： H04N5/765 ,  G06F3/1431 ,  G06F3/1438 ,  G09G5/005 ,  G09G5/006 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2340/0485 ,  G09G2360/18 ,  G09G2370/045 ,  G09G2370/20 ,  H04N5/46 ,  H04N21/4122 ,  H04N21/4143 ,  H04N21/4402 ,  H04N21/4436 ,  H04N21/4622

    摘要： An information handling system includes a video processor that provides a first video signal in a first video format; a display that receives a second video signal in a second video format; and another display that receives a third video signal in a third video format. The first, second, and third video formats are all different from each other. The information handling system also includes a mid-stream frame buffer that stores video information from the first, second, and third video signals, and a video selector coupled to the mid-stream frame buffer the video processor and the displays. The video selector converts the First video signal into the second and third video signals and couples the video processor to a selected display.

    摘要翻译： 信息处理系统包括以第一视频格式提供第一视频信号的视频处理器; 以第二视频格式接收第二视频信号的显示器; 以及以第三视频格式接收第三视频信号的另一显示器。 第一，第二和第三视频格式彼此不同。 信息处理系统还包括中流帧缓冲器，其存储来自第一，第二和第三视频信号的视频信息，以及耦合到视频处理器和显示器的中间流帧缓冲器的视频选择器。 视频选择器将第一视频信号转换为第二和第三视频信号，并将视频处理器耦合到选定的显示器。

    System and method for dynamic adjustment of an information handling systems graphics bus
    9.
    发明授权
    System and method for dynamic adjustment of an information handling systems graphics bus 有权
    用于动态调整信息处理系统图形总线的系统和方法

    公开(公告)号：US07539809B2

    公开(公告)日：2009-05-26

    申请号：US11207298

    申请日：2005-08-19

    申请人： Randall E. Juenger

    发明人： Randall E. Juenger

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4063 ,  G06F13/40 ,  Y02D10/14 ,  Y02D10/151

    摘要： PCI Express bus utilization is monitored for one or more predetermined thresholds to adjust the width of the bus in accordance with the utilization to provide power savings with minimal impact on performance. For instance, a performance monitor of a graphics controller tracks bus utilization with registers to adjust bus width between one, eight and sixteen lanes. Reduced numbers of active lanes are used at low utilization, such as one lane when a desktop graphic is presented on the display, increased numbers of active lanes are used at moderate utilization, such as eight lanes when a video image is presented on the display, and all lanes are active at high utilization, such as for presentation of three dimensional images.

    摘要翻译： 对一个或多个预定阈值监视PCI Express总线利用率，以根据利用率来调整总线的宽度，从而以最小的性能影响提供功率节省。 例如，图形控制器的性能监视器通过寄存器跟踪总线利用率，以调整一个，八个和十六个车道之间的总线宽度。 在低利用率下使用减少的活动车道数量，例如当在显示器上呈现桌面图形时的一个车道，在中等利用率下使用增加的活动车道数量，例如当显示器上呈现视频图像时的八个车道， 并且所有车道在高利用率下是活跃的，例如呈现三维图像。