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    Voltage level shifter with single well voltage
    4.
    发明申请
    Voltage level shifter with single well voltage 有权
    具有单井电压的电压电平转换器

    公开(公告)号：US20080143418A1

    公开(公告)日：2008-06-19

    申请号：US11639006

    申请日：2006-12-14

    申请人： Lee-Chung Lu ,  Chung-Hsing Wang ,  Chun-Hui Tai ,  Li-Chun Tien ,  Shun-Li Chen

    发明人： Lee-Chung Lu ,  Chung-Hsing Wang ,  Chun-Hui Tai ,  Li-Chun Tien ,  Shun-Li Chen

    IPC分类号： H03L5/00

    CPC分类号： H03K3/35613

    摘要： This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

    摘要翻译： 本发明公开了一种电压电平转换器，它包括具有栅极，源极和体耦合到输入端的第一P型金属氧化物半导体（PMOS）晶体管，第一正电压电源和第二正电压 电源，以及分别具有源极，漏极和体耦合到第三正电压电源，输出节点和第二正电压电源的第二PMOS晶体管，其中形成第一和第二PMOS晶体管 在一个Nwell。

    Standard Cell without OD Space Effect in Y-Direction
    5.
    发明申请
    Standard Cell without OD Space Effect in Y-Direction 有权
    标准电池在Y方向没有OD空间效应

    公开(公告)号：US20100078725A1

    公开(公告)日：2010-04-01

    申请号：US12345372

    申请日：2008-12-29

    申请人： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    发明人： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    IPC分类号： H01L27/088 ,  H01L29/06

    CPC分类号： H01L27/0207 ,  H01L27/11807

    摘要： An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.

    摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底中的第一有源区; 以及在所述半导体衬底中并且具有与所述第一有源区相反的导电类型的第二有源区。 栅电极条在第一和第二有源区之上，分别形成具有第一有源区和第二有源区的第一MOS器件和第二MOS器件。 第一间隔棒位于半导体衬底中并与第一有源区连接。 第一间隔条的至少一部分与第一有源区的一部分相邻并间隔开。 第二间隔杆位于半导体衬底中并连接到第二有源区。 第二间隔杆的至少一部分与第二有源区的一部分相邻并间隔开。

    Layout architecture for improving circuit performance
    6.
    发明授权
    Layout architecture for improving circuit performance 有权
    用于提高电路性能的布局架构

    公开(公告)号：US07821039B2

    公开(公告)日：2010-10-26

    申请号：US12193354

    申请日：2008-08-18

    申请人： Li-Chun Tien ,  Lee-Chung Lu ,  Yung-Chin Hou ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Sheng-Hsin Chen ,  Ping Chung Li

    发明人： Li-Chun Tien ,  Lee-Chung Lu ,  Yung-Chin Hou ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Sheng-Hsin Chen ,  Ping Chung Li

    IPC分类号： H01L27/10 ,  H01L23/62 ,  H01L29/76 ,  H01L29/94 ,  H01L29/00

    CPC分类号： H01L27/092 ,  H01L27/0207

    摘要： An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.

    摘要翻译： 集成电路结构包括集成电路结构，其包括：包括第一栅电极的PMOS晶体管; 第一源区; 和第一漏区; 包括第二栅电极的NMOS晶体管，其中所述第一栅电极和所述第二栅电极是栅电极条的部分; 第二源区; 和第二漏区。 在PMOS晶体管和NMOS晶体管之间不会形成附加的晶体管。 集成电路还包括连接到第一源极区的VDD电源轨; 连接到第二源区的VSS电力轨; 以及电连接到栅电极条的互连端口。 互连端口位于包括PMOS晶体管，NMOS晶体管以及PMOS晶体管和NMOS晶体管之间的区域的MOS对区域的外侧。 MOS对区域中的栅电极条的部分基本上是直的。

    Layout Architecture for Improving Circuit Performance
    7.
    发明申请
    Layout Architecture for Improving Circuit Performance 有权
    用于提高电路性能的布局架构

    公开(公告)号：US20090315079A1

    公开(公告)日：2009-12-24

    申请号：US12193354

    申请日：2008-08-18

    申请人： Li-Chun Tien ,  Lee-Chung Lu ,  Yung-Chin Hou ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Sheng-Hsin Chen ,  Ping Chung Li

    发明人： Li-Chun Tien ,  Lee-Chung Lu ,  Yung-Chin Hou ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Sheng-Hsin Chen ,  Ping Chung Li

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/092 ,  H01L27/0207

    摘要： An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.

    摘要翻译： 集成电路结构包括集成电路结构，其包括：包括第一栅电极的PMOS晶体管; 第一源区; 和第一漏区; 包括第二栅电极的NMOS晶体管，其中所述第一栅电极和所述第二栅电极是栅电极条的部分; 第二源区; 和第二漏区。 在PMOS晶体管和NMOS晶体管之间不会形成附加的晶体管。 集成电路还包括连接到第一源极区的VDD电源轨; 连接到第二源区的VSS电力轨; 以及电连接到栅电极条的互连端口。 互连端口位于包括PMOS晶体管，NMOS晶体管以及PMOS晶体管和NMOS晶体管之间的区域的MOS对区域的外侧。 MOS对区域中的栅电极条的部分基本上是直的。

    Standard cell without OD space effect in Y-direction
    8.
    发明授权
    Standard cell without OD space effect in Y-direction 有权
    标准电池在Y方向没有OD空间效应

    公开(公告)号：US07808051B2

    公开(公告)日：2010-10-05

    申请号：US12345372

    申请日：2008-12-29

    申请人： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    发明人： Yung-Chin Hou ,  Lee-Chung Lu ,  Ta-Pen Guo ,  Li-Chun Tien ,  Ping Chung Li ,  Chun-Hui Tai ,  Shu-Min Chen

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0207 ,  H01L27/11807

    摘要： An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.

    摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底中的第一有源区; 以及在所述半导体衬底中并且具有与所述第一有源区相反的导电类型的第二有源区。 栅电极条在第一和第二有源区之上，分别形成具有第一有源区和第二有源区的第一MOS器件和第二MOS器件。 第一间隔棒位于半导体衬底中并与第一有源区连接。 第一间隔条的至少一部分与第一有源区的一部分相邻并间隔开。 第二间隔杆位于半导体衬底中并连接到第二有源区。 第二间隔杆的至少一部分与第二有源区的一部分相邻并间隔开。

    NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT
    9.
    发明申请
    NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT 审中-公开
    性能增强的新型布局架构

    公开(公告)号：US20100127333A1

    公开(公告)日：2010-05-27

    申请号：US12276172

    申请日：2008-11-21

    申请人： Yung-Chin Hou ,  Ta-Pen Guo ,  Harry Chuang ,  Carlos H. Diaz ,  Lee-Chung Lu ,  Li-Chun Tien ,  Oscar M. K. Law ,  Chih-Chiang Chang ,  Chun-Hui Tai ,  Jonathan Lee

    发明人： Yung-Chin Hou ,  Ta-Pen Guo ,  Harry Chuang ,  Carlos H. Diaz ,  Lee-Chung Lu ,  Li-Chun Tien ,  Oscar M. K. Law ,  Chih-Chiang Chang ,  Chun-Hui Tai ,  Jonathan Lee

    IPC分类号： H01L27/092 ,  H01L27/088

    CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823481

    摘要： The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate.

    摘要翻译： 本发明提供集成电路。 集成电路包括半导体衬底中的有源区; 设置在有源区中的第一场效应晶体管（FET） 以及设置在有源区域中的隔离结构。 FET包括第一栅极; 形成在所述有源区中并且从第一侧设置在与所述第一栅极相邻的第一区域上的第一源极; 以及形成在所述有源区中并且从第二侧设置在与所述第一栅极相邻的第二区域上的第一漏极。 隔离结构包括邻近第一漏极设置的隔离栅极; 以及隔离源，形成在所述有源区中并邻近所述隔离栅设置，使得所述隔离源和所述第一漏极位于所述隔离栅极的不同侧上。

    Integrated circuit design using DFM-enhanced architecture
    10.
    发明授权
    Integrated circuit design using DFM-enhanced architecture 有权
    采用DFM增强架构的集成电路设计

    公开(公告)号：US08631366B2

    公开(公告)日：2014-01-14

    申请号：US12708242

    申请日：2010-02-18

    申请人： Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    发明人： Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.

    摘要翻译： 集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。 第一标准细胞和第二标准细胞具有相同的细胞变体。 第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。 第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。