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    Spacer structures of a semiconductor device
    1.
    发明授权
    Spacer structures of a semiconductor device 有权
    半导体器件的间隔结构

    公开(公告)号：US08304840B2

    公开(公告)日：2012-11-06

    申请号：US12846261

    申请日：2010-07-29

    申请人： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

    发明人： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

    IPC分类号： H01L21/02 ,  H01L21/70 ,  H01L27/088

    CPC分类号： H01L29/401 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088

    摘要： The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.

    摘要翻译： 本公开涉及半导体器件的间隔结构。 半导体器件的示例性结构包括具有第一有源区和第二有源区的衬底; 多个在所述第一有源区上具有栅间距的第一栅电极，其中每个第一栅电极具有第一宽度; 与所述多个第一栅电极相邻的多个第一间隔件，其中每个第一间隔件具有第三宽度; 多个第二栅电极，其具有与第二有源区上的多个第一栅电极相同的栅极间距，其中每个第二栅电极具有大于第一宽度的第二宽度; 以及与所述多个第二栅电极相邻的多个第二间隔件，其中每个第二间隔件具有小于所述第三宽度的第四宽度。

    Metal gate structure of a CMOS semiconductor device
    2.
    发明授权
    Metal gate structure of a CMOS semiconductor device 有权
    CMOS半导体器件的金属栅极结构

    公开(公告)号：US08183644B1

    公开(公告)日：2012-05-22

    申请号：US13025956

    申请日：2011-02-11

    申请人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Ming Zhu ,  Hui-Wen Lin ,  Lee-Wee Teo

    发明人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Ming Zhu ,  Hui-Wen Lin ,  Lee-Wee Teo

    IPC分类号： H01L21/027

    CPC分类号： H01L21/823842 ,  H01L21/823871

    摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising a P-active region, an N-active region, and an isolation region interposed between the P- and N-active regions; a P-metal gate electrode over the P-active region, that extends over the isolation region; and an N-metal gate electrode having a first width over the N-active region, that extends over the isolation region and has a contact section in the isolation region electrically contacting the P-metal gate electrode, wherein the contact section has a second width greater than the first width.

    摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，其包括P活性区域，N活性区域和插入在P-活性区域和N - 活性区域之间的隔离区域; 在P-活性区域上的P金属栅极电极，其在隔离区域上延伸; 以及在所述N-有源区上具有第一宽度的N-金属栅电极，其在所述隔离区上延伸，并且在所述隔离区中具有与所述P金属栅电极电接触的接触部，其中所述接触部具有第二宽度 大于第一宽度。

    METAL GATE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THEREOF
    4.
    发明申请
    METAL GATE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THEREOF 有权
    金属栅极半导体器件及其制造方法

    公开(公告)号：US20130256805A1

    公开(公告)日：2013-10-03

    申请号：US13434969

    申请日：2012-03-30

    申请人： Hak-Lay Chuang ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young

    发明人： Hak-Lay Chuang ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young

    IPC分类号： H01L27/092 ,  H01L21/283

    CPC分类号： H01L29/4966 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

    摘要： A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer.

    摘要翻译： 一种半导体制造方法，包括在所述基板的第一区域上形成第一功函数金属层，并在所述第一功函数金属层上和所述基板的第二区域上形成金属层。 在金属层上形成虚设层。 然后将这些层图案化以在第一区域中形成第一栅极结构，在衬底的第二区域中形成第二栅极结构。 然后去除虚拟层以暴露被处理的金属层。 处理可以是允许金属层用作第二功函数层的氧处理。

    Metal gate semiconductor device and method of fabricating thereof
    5.
    发明授权
    Metal gate semiconductor device and method of fabricating thereof 有权
    金属栅极半导体器件及其制造方法

    公开(公告)号：US08772114B2

    公开(公告)日：2014-07-08

    申请号：US13434969

    申请日：2012-03-30

    申请人： Hak-Lay Chuang ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young

    发明人： Hak-Lay Chuang ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/4966 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

    摘要： A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer.

    摘要翻译： 一种半导体制造方法，包括在所述基板的第一区域上形成第一功函数金属层，并在所述第一功函数金属层上和所述基板的第二区域上形成金属层。 在金属层上形成虚设层。 然后将这些层图案化以在第一区域中形成第一栅极结构，在衬底的第二区域中形成第二栅极结构。 然后去除虚拟层以暴露被处理的金属层。 处理可以是允许金属层用作第二功函数层的氧处理。