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公开(公告)号：US5287477A
公开(公告)日：1994-02-15
申请号：US741703
申请日：1991-08-07
CPC分类号： G06F13/161 , G06F12/0607
摘要： A method and apparatus to improve memory performance in a computer bus system. Memory is divided into interleaved blocks and memory addresses are mapped into block identification numbers. Master devices keep track of which parts of memory are busy by storing memory block identification numbers in local queues whenever memory is accessed. Block identification numbers are removed from local queues when the memory transaction is complete. Master devices arbitrate for access to the bus for memory transactions only if the target memory block identification number is not in the local queue.
摘要翻译： 一种用于改善计算机总线系统中的存储器性能的方法和装置。 存储器被划分为交错块，存储器地址被映射到块标识号。 当存储器被访问时，主设备通过将存储器块识别号码存储在本地队列中来跟踪存储器的哪个部分正在占用。 当内存事务完成时，块标识号从本地队列中删除。 只有当目标存储器块标识号不在本地队列中时，主设备仲裁才能访问总线用于存储器事务。
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2.发明授权Decreasing average time to access a computer bus by eliminating arbitration delay when the bus is idle 失效当总线空闲时，通过消除仲裁延迟，减少访问计算机总线的平均时间
公开(公告)号：US5255373A
公开(公告)日：1993-10-19
申请号：US741712
申请日：1991-08-07
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： A method and apparatus to improve computer bus access time. A bus is described which has sequential control states and fixed transaction times. Without the invention, arbitration may be delayed as the bus sequences through control states. With the invention, arbitration is immediate if the bus is idle. When any transaction is initiated, a counter is initialized to the number of control states in the standard transaction time. If the counter reaches zero, the bus is idle. If the bus is not idle, a sequence of bus control states is repeated. If the bus is idle, the bus is forced to remain in an arbitration state, thereby enabling any subsequent arbitration to take place immediately.
摘要翻译： 一种提高计算机总线访问时间的方法和装置。 描述了具有顺序控制状态和固定交易时间的总线。 没有本发明，可以通过控制状态作为总线序列来延迟仲裁。 利用本发明，如果总线空闲，则立即进行仲裁。 当任何事务被启动时，计数器被初始化为标准事务时间中的控制状态数。 如果计数器达到零，则总线空闲。 如果总线不空闲，则重复一系列总线控制状态。 如果总线空闲，则总线被迫保持在仲裁状态，从而使之能够立即进行后续仲裁。
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公开(公告)号：US5265223A
公开(公告)日：1993-11-23
申请号：US924423
申请日：1992-07-31
IPC分类号： G06F13/368 , G06F13/00 , G06F13/36
CPC分类号： G06F13/368
摘要： A method and circuitry for controlling priority of devices contending for access to a data communications link. Each device capable of contending for access contains a priority register which indicates the relative priority of every device capable of contending for access. After gaining access to the link, a device may optionally signal to all devices to update priority. When priority is updated, the device signaling priority update is moved to lowest priority. Inhibiting the signal to update priority permits a device to maintain priority. Systems using the method may be configured with a fair arbitration protocol (least recently accessed has highest priority), with fixed priority protocol, or with priority protocols that can be modified in real time.
摘要翻译： 一种用于控制竞争访问数据通信链路的设备的优先级的方法和电路。 能够争取访问的每个设备都包含优先级寄存器，该优先级寄存器指示每个能够竞争访问的设备的相对优先级。 在访问链接之后，设备可以可选地向所有设备发信号以更新优先级。 当优先级更新时，设备信令优先级更新被移动到最低优先级。 抑制信号更新优先级允许设备保持优先级。 使用该方法的系统可以配置有公平的仲裁协议（最近访问的具有最高优先级），具有固定优先级协议，或者可以实时修改的优先级协议。
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4.发明授权Method of reducing wasted bus bandwidth due to slow responding slaves in a multiprocessor computer system 失效在多处理器计算机系统中由于缓慢响应的从站而减少浪费的总线带宽的方法
公开(公告)号：US5257356A
公开(公告)日：1993-10-26
申请号：US705873
申请日：1991-05-28
IPC分类号： G06F13/36 , G06F9/52 , G06F13/362 , G06F13/368 , G06F15/16 , G06F15/177
CPC分类号： G06F13/368
摘要： In a multiprocessor computer system, wasted bus bandwidth resulting from slow responding slaves is reduced by relinquishing the master that was busied by the slow responding slave, and then causing the slave to effectively arbitrate for bus control on the relinquished master's behalf when the slow responding slave is either available to service the master or has the requested data. In accordance with the disclosed embodiment, the slave effectively arbitrates for bus control on the relinquished master's behalf by placing a unique arbitration code associated with the relinquished master on the bus. The relinquished master detects the presence of its arbitration code and then again arbitrates for bus control so that it may communicate with the slow responding slave.
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5.发明授权
公开(公告)号：US5249297A
公开(公告)日：1993-09-28
申请号：US694265
申请日：1991-04-29
IPC分类号： G06F13/36 , G06F12/08 , G06F13/368 , G06F15/17
CPC分类号： G06F15/17 , G06F12/0831 , G06F13/368
摘要： A protocol for carrying out transactions in a multiple-processor computer system comprises: dividing the transaction cycle into four quadrature states, an arbitrate state, an I/O state, a slave address state and a virtual memory state. The protocol enables the processors to determine before arbitrating whether the memory device is busy, which reduces the number of "busied" transactions.
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公开(公告)号：US5293607A
公开(公告)日：1994-03-08
申请号：US679868
申请日：1991-04-03
IPC分类号： G06F12/06 , G11C11/401 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0607
摘要： The invention comprises methods and apparatuses for interleaving a number of memory cards of different sizes. A restricted range modulo-N adder for identifying and selecting the correct interleave card is provided. Another aspect of the invention provides a computer system with flexible memory interleaving capability.
摘要翻译： 本发明包括用于交织不同大小的多个存储卡的方法和装置。 提供了用于识别和选择正确交错卡的限制范围模N加法器。 本发明的另一方面提供一种具有灵活的存储器交错能力的计算机系统。
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公开(公告)号：US5881217A
公开(公告)日：1999-03-09
申请号：US758606
申请日：1996-11-27
CPC分类号： G06F7/764 , G06F7/02 , G06F9/30043 , G06F9/30098 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： Method for decoding inputs in a programmable state machine, including the following steps: bit-wise comparing state machine inputs with select information to produce bit-wise comparison results; determining the logical AND of the bit-wise comparison results; and determining the logical EXCLUSIVE OR of a negate indicator and the logical AND. In a further embodiment, a step of bit-wise ORing the comparison results with mask information is performed before the logical AND step. Circuitry for implementing the method: A bit-wise comparator has two sets of inputs. Its first set of inputs is coupled to state machine input signals. Its second set of inputs is coupled to select information. It is operable to produce bit-wise comparator outputs that indicate the results of bit-wise comparing the state machine input signals with the select information. AND circuitry has an AND circuitry output to indicate the logical AND of the comparator outputs. An EXCLUSIVE OR gate has its first input coupled to the AND circuitry output and has its second input coupled to a negate indicator. The output of the EXCLUSIVE OR gate constitutes the output of the inventive input comparison circuitry. In further embodiments, bit-wise OR circuitry may be interposed between the comparator and the AND circuitry. Such bit-wise OR circuitry may be used for masking by coupling its first set of inputs to the comparator outputs and coupling its second set of inputs to mask information. In the latter embodiment, the bit-wise results of the OR circuitry are ANDed by the AND circuitry.
摘要翻译： 用于对可编程状态机中的输入进行解码的方法，包括以下步骤：将状态机输入与选择信息进行比特比较，以产生逐位比较结果; 确定比特比较结果的逻辑AND; 并且确定否定指示符和逻辑AND的逻辑异或。 在另一实施例中，在逻辑与步骤之前执行将比较结果与掩码信息进行逐位OR比较的步骤。 实现该方法的电路：比特比较器具有两组输入。 其第一组输入端连接到状态机输入信号。 其第二组输入耦合到选择信息。 它可操作地产生逐位比较器输出，其指示将状态机输入信号与选择信息进行逐位比较的结果。 AND电路具有AND电路输出，用于指示比较器输出的逻辑AND。 独占或门的第一个输入端连接到AND电路输出，并将其第二个输入端耦合到一个否定指示器。 EXCLUSIVE OR门的输出构成本发明的输入比较电路的输出。 在另外的实施例中，可以在比较器和AND电路之间插入逐位OR电路。 这种逐位OR电路可以用于通过将其第一组输入耦合到比较器输出并将其第二组输入耦合到掩模信息来进行掩蔽。 在后一实施例中，OR电路的逐位结果由AND电路进行“与”运算。
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公开(公告)号：US06789186B1
公开(公告)日：2004-09-07
申请号：US09507038
申请日：2000-02-18
IPC分类号： G06G900
CPC分类号： G06F9/3804 , G06F9/30174
摘要： A method and apparatus are provided for improving the rate at which macroinstructions are transformed into corresponding microinstructions. Encoding is added to a microcode storage device. The encoding indicates that a microinstruction flow will end in a determined number of cycles. The number of cycles is determined by the number of canceled instructions in a processing pipeline that would be introduced if no flow length prediction was used. For flow lengths less than a determined number of cycles, a hint bit is used in an entry point structure. For flow lengths greater than a determined length, a hint bit is encoded at a third line from an end of the microinstruction flow. Using this method, flows of any length can be hinted. Furthermore, flows that do not originate from the entry point structure can also be hinted. The method reduces the number of hint bits that are needed in the entry point structure and provides for better prediction.
摘要翻译： 提供了一种方法和装置，用于提高宏指令转换成相应微指令的速率。 编码被添加到微代码存储设备中。 编码指示微指令流将以确定的周期数结束。 循环数由在不使用流量长度预测的情况下将被引入的处理流水线中的取消指令的数量来确定。 对于小于一定数量的循环的流量长度，在入口点结构中使用提示位。 对于大于确定长度的流量长度，提示位在微指令流的末尾的第三行编码。 使用这种方法，可以暗示任何长度的流。 此外，也可以暗示不源于入口点结构的流。 该方法减少了入口点结构中所需的提示位的数量，并提供了更好的预测。
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9.发明授权Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit 有权用于验证中央处理器单元的行为模型的细粒度正确性的方法和装置公开(公告)号：US06625759B1
公开(公告)日：2003-09-23
申请号：US09502366
申请日：2000-02-18
申请人： Jeremy Petsinger , Kevin David Safford , Karl P. Brummel , Russell C. Brockmann , Bruce A. Long , Patrick Knebel
发明人： Jeremy Petsinger , Kevin David Safford , Karl P. Brummel , Russell C. Brockmann , Bruce A. Long , Patrick Knebel
IPC分类号： H02H305
CPC分类号： G06F11/261
摘要： A method and an apparatus checks the fine-grain correctness of a microcode machine central processor unit (CPU) behavioral model. Macroinstructions are decomposed into microinstructions and each microinstruction is executed sequentially. A sequence of microinstructions is determined by an emulated microinstruction sequencer, using dynamic execution information, including information from execution of prior microinstructions in the sequence of microinstructions. At the end of execution of each microinstruction, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted. After execution of all microinstructions in the microinstruction sequence, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted.
摘要翻译： 一种方法和装置检查微码机中央处理器单元（CPU）行为模型的细粒度正确性。 宏指令被分解为微指令，并且每个微指令都被顺序执行。 微指令序列由模拟的微指令测序仪确定，使用动态执行信息，包括在微指令序列中执行先前微指令的信息。 在每个微指令的执行结束时，将参考状态与行为模型的相应状态进行比较，并且注意到任何差异。 在微指令序列中执行所有微指令之后，将参考状态与行为模型的相应状态进行比较，并记录任何差异。
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10.发明授权Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle 失效用于跟踪微处理器中的事件的装置和方法，其可以在时钟周期期间退出多于一个指令
公开(公告)号：US5881224A
公开(公告)日：1999-03-09
申请号：US711574
申请日：1996-09-10
CPC分类号： G06F9/3865 , G06F11/076 , G06F11/2236 , G06F11/348 , G06F9/30032 , G06F9/30101 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F11/3409 , G06F2201/88
摘要： In one embodiment, the invention includes a method of tracking events in a microprocessor that can retire more than one instruction during a clock cycle. A set of match results is generated during each clock cycle, one match result for each retiring instruction. Each of the match results indicates whether the corresponding retiring instruction matched a criterion. Then, the total number of retiring instruction that matched the criterion is determined by adding the asserted match results to generate a sum. A counter is incremented by the sum. In another embodiment, the invention includes circuitry for implementing the just-described method. Match generator circuitry is provided for generating a set of match results during each clock cycle, one match result for each retiring instruction. The outputs of the match generator circuitry are supplied to adder circuitry. The adder circuitry is operable to determine the number of said match results that are asserted and to represent the number as a sum via a set of adder circuitry outputs. A counter having a set of adder circuitry inputs is coupled to adder circuitry outputs. The counter is operable to increment its count by the sum represented by the adder circuitry outputs. In further embodiments, a multiplexer is interposed between the adder circuitry and the counter. The multiplexer has a first set of inputs coupled to the adder circuitry outputs, and a second set of inputs coupled to a source of the value "1." The multiplexer is operable to present either the first or second inputs on its outputs responsive to a select signal. The multiplexer has its outputs coupled to the increment inputs of the counter.
摘要翻译： 在一个实施例中，本发明包括跟踪微处理器中的事件的方法，其可以在时钟周期期间退出多于一个指令。 在每个时钟周期内产生一组匹配结果，每个退出指令一个匹配结果。 每个匹配结果指示相应的退出指令是否匹配标准。 然后，通过添加所断言的匹配结果以产生和来确定与标准匹配的退休指令的总数。 一个计数器增加一个和。 在另一个实施例中，本发明包括用于实现刚刚描述的方法的电路。 匹配发生器电路被提供用于在每个时钟周期期间产生一组匹配结果，每个退出指令的一个匹配结果。 匹配发生器电路的输出被提供给加法器电路。 加法器电路可操作以确定所确定的所述匹配结果的数量，并且经由一组加法器电路输出将数字表示为和。 具有一组加法器电路输入的计数器耦合到加法器电路输出。 计数器可操作地将其计数增加由加法器电路输出表示的和。 在另外的实施例中，多路复用器插在加法器电路和计数器之间。 多路复用器具有耦合到加法器电路输出的第一组输入和耦合到值“1”的源的第二组输入。 多路复用器可操作以响应于选择信号在其输出上呈现第一或第二输入。 多路复用器的输出端与计数器的增量输入相连。
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