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公开(公告)号：US09270294B2
公开(公告)日：2016-02-23
申请号：US14763450
申请日：2014-01-24
发明人： Dirk Duesterberg , Heiko Stichweh
摘要： A method is provided for generating a digital signal from an analog signal generated using a frequency converter on the basis of pulse width modulation with a variable period duration, values of the digital signal corresponding to an average value of the analog signal over an associated period duration of the pulse width modulation. The method includes the acts of: generating a bit stream on the basis of the analog signal using a sigma-delta modulator, the bit stream being generated with a constant modulator clock; generating temporally successive digital samples during an associated period duration by filtering the bit stream using a number of digital filters, intervals of time between the temporally successive digital samples being multiples of the modulator clock, the digital filters being started with a time delay with respect to one another in the intervals of time of the multiples of the modulator clock, and a respective digital filter outputting an associated digital sample, and forming an average value of the digital samples generated during the associated period duration, the average value forming the value of the digital signal (DS) for the associated period duration.
摘要翻译： 提供一种方法，用于根据具有可变周期持续时间的脉冲宽度调制从使用频率转换器产生的模拟信号产生数字信号，数字信号的值对应于模拟信号在相关联的周期持续时间内的平均值 的脉宽调制。 该方法包括以下动作：基于使用Σ-Δ调制器的模拟信号产生比特流，该比特流由恒定的调制器时钟产生; 通过使用多个数字滤波器对位流进行滤波来在相关联的周期持续时间内产生时间上连续的数字采样，时间上连续的数字采样之间的时间间隔是调制器时钟的倍数，数字滤波器以相对于 在调制器时钟的倍数的时间间隔中相互对应的数字滤波器，以及相应的数字滤波器，输出相关联的数字样本，并形成在相关联的周期持续时间期间产生的数字样本的平均值， 数字信号（DS）。
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公开(公告)号：US10705991B2
公开(公告)日：2020-07-07
申请号：US16482074
申请日：2018-01-29
发明人： Dirk Duesterberg
摘要： A circuit for generating a sampling signal for a UART interface has an input terminal designed to receive a peripheral clock, an output terminal designed to output the sampling signal, a bit rate memory designed to store a value corresponding to a desired bit rate of the UART interface, a peripheral clock memory designed to store a value corresponding to a frequency of the peripheral clock, a sum memory designed to store a sum value, and a computing unit. The computing unit compares a comparison value, which is dependent on the sum value stored in the sum memory, with a threshold value, which is dependent on the value stored in the peripheral clock memory. The result of the comparison is taken as a basis for generating the sampling signal at a first level or a second level. In step with the peripheral clock and on the basis of the result of the comparing, the sum value stored in the sum memory is altered by the value stored in the bit rate memory or the sum value stored in the sum memory is altered by a value that is dependent on the value stored in the peripheral clock memory.
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公开(公告)号：US11880177B2
公开(公告)日：2024-01-23
申请号：US16967603
申请日：2019-02-05
发明人： Dirk Duesterberg
IPC分类号： G05B15/02
CPC分类号： G05B15/02
摘要： A controller for controlling an electric motor includes an interface having a first connection pole and a second connection pole, wherein the interface is designed to connect a measuring resistor and to connect a digital encoder. The controller is designed to evaluate a resistance value of the measuring resistor in order to monitor the temperature of the electric motor when the measuring resistor is connected to the interface, and the controller is designed to receive digital data from the digital encoder at the interface when the digital encoder is connected to the interface.
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公开(公告)号：US10348325B2
公开(公告)日：2019-07-09
申请号：US15998540
申请日：2018-08-16
发明人： Dirk Duesterberg
摘要： A measuring device includes a delta-sigma modulator configured to take an analog signal as a basis for generating a bit stream, and an evaluation unit that receives the bit stream from the delta-sigma modulator and evaluates the received bit stream. The measuring device has a single data transmission line, wherein the delta-sigma modulator is configured to transmit the bit stream to the evaluation unit via the single data transmission line using a transmit clock, and wherein the evaluation unit is configured to reconstruct the transmit clock and/or a phase of bits within the bit stream from the received bit stream and to extract the bits from the received bit stream based on the reconstructed transmit clock and/or based on the reconstructed phase.
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公开(公告)号：US11287790B2
公开(公告)日：2022-03-29
申请号：US16641389
申请日：2018-08-02
发明人： Peter Hesse , Dirk Duesterberg , Thomas Gentzen
IPC分类号： G05B19/04 , G05B19/042
摘要： A method for starting up a controller system having at least one electric controller and a plurality of hardware modules of different types which can be coupled to the controller. To each type of hardware module there is assigned a type-specific parameter set and a type-specific control program. A respective parameter set has a quantity of parameters with adjustable parameter values. The method has the steps of: coupling a hardware module to the controller, determining the type of the coupled hardware module by way of the controller, selecting the type-specific control program by way of the controller, and by way of the controller, selecting the type-specific parameter set as an adjustable parameter set.
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公开(公告)号：US10910956B2
公开(公告)日：2021-02-02
申请号：US15746738
申请日：2016-07-19
发明人： Fritz Witte , Thomas Petersen , Dirk Duesterberg
IPC分类号： H02M7/5387 , H02P27/14 , H02P27/08
摘要： A method is provided for operating a frequency converter, which is designed to drive a three-phase motor, wherein the frequency converter has three half-bridges each having at least two switches. The method includes the following steps: generating three phase voltages for the three-phase motor by a pulse width modulation, wherein, for the pulse width modulation, various switching patterns of the switches are activated, wherein specific star point voltages ensue for various groups of switching patterns; and in at least one operating state of the frequency converter, within a respective period of the pulse width modulation, activating only those switching patterns in which an identical star point voltage ensues.
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公开(公告)号：US10784889B2
公开(公告)日：2020-09-22
申请号：US16629796
申请日：2018-07-09
摘要： An electric control device includes a first delta sigma modulator having a clock input connection, a second delta sigma modulator having a clock input connection, and an evaluation unit. The evaluation unit includes a first clock output connection which is connected to the clock input connection of the first delta sigma modulator by a first electrical cable, and a second clock output connection which is connected to the clock input connection of the second delta sigma modulator by a second electrical cable. The evaluation unit is designed to generate a clock signal (CLK1) at the first clock output connection (7) in phase opposition to a clock signal (CLK2) at the second clock output connection (9).
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公开(公告)号：US20190058488A1
公开(公告)日：2019-02-21
申请号：US15998540
申请日：2018-08-16
发明人： Dirk Duesterberg
IPC分类号： H03M3/00
CPC分类号： H03M3/458 , G08C13/00 , G08C2200/00 , H03M1/1071 , H03M1/12 , H03M3/43 , H03M7/304 , H04B14/062 , H04Q2209/30 , H04Q2209/84
摘要： A measuring device includes a delta-sigma modulator configured to take an analog signal as a basis for generating a bit stream, and an evaluation unit that receives the bit stream from the delta-sigma modulator and evaluates the received bit stream. The measuring device has a single data transmission line, wherein the delta-sigma modulator is configured to transmit the bit stream to the evaluation unit via the single data transmission line using a transmit clock, and wherein the evaluation unit is configured to reconstruct the transmit clock and/or a phase of bits within the bit stream from the received bit stream and to extract the bits from the received bit stream based on the reconstructed transmit clock and/or based on the reconstructed phase.
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