公开(公告)号：US07478301B2

公开(公告)日：2009-01-13

申请号：US12114198

申请日：2008-05-02

申请人： Leonard O. Farnsworth, III ,  Michael Z. Felske ,  Pamela S. Gillis ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St. Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

发明人： Leonard O. Farnsworth, III ,  Michael Z. Felske ,  Pamela S. Gillis ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St. Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

IPC分类号： G01R31/28

CPC分类号： G01R31/318558 ,  G01R31/318505 ,  G01R31/318516 ,  G11C2029/1208 ,  G11C2029/3202

摘要： An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

摘要翻译： 集成电路的测试和维修的集成电路和方法。 集成电路包括：具有相同功能的多个宏电路; 保险丝库，保险丝的状态存储测试数据，至少指示哪些宏观电路未通过测试; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏 具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的熔丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

公开(公告)号：US07305600B2

公开(公告)日：2007-12-04

申请号：US10651874

申请日：2003-08-29

申请人： Leonard O. Farnsworth, III ,  Michael Z. Felske ,  Pamela S. Gillis ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St.Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

发明人： Leonard O. Farnsworth, III ,  Michael Z. Felske ,  Pamela S. Gillis ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St.Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

IPC分类号： G01R31/28

CPC分类号： G01R31/318558 ,  G01R31/318505 ,  G01R31/318516 ,  G11C2029/1208 ,  G11C2029/3202

摘要： An integrated circuit, including: a multiplicity of macro-circuits, each macro-circuit having the same function; a fuse bank containing a multiplicity of fuses, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

摘要翻译： 一种集成电路，包括：多个宏电路，每个宏电路具有相同的功能; 包含多个保险丝的保险丝库，保险丝的状态存储测试数据，至少指示哪些宏电路测试失败; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏 具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的熔丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

公开(公告)号：US07434129B2

公开(公告)日：2008-10-07

申请号：US11859834

申请日：2007-09-24

申请人： Leonard O. Farnsworth, III ,  Michael Z. Felske ,  Pamela S. Gillia ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St. Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

发明人： Leonard O. Farnsworth, III ,  Michael Z. Felske ,  Pamela S. Gillia ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St. Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

IPC分类号： G01R31/28

CPC分类号： G01R31/318558 ,  G01R31/318505 ,  G01R31/318516 ,  G11C2029/1208 ,  G11C2029/3202

摘要： An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

摘要翻译： 集成电路的测试和修复的集成电路和方法。 集成电路包括：具有相同功能的多个宏电路; 保险丝库，保险丝的状态存储测试数据，至少指示哪些宏观电路未通过测试; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏 具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的熔丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

公开(公告)号：US20080209289A1

公开(公告)日：2008-08-28

申请号：US12114198

申请日：2008-05-02

申请人： Leonard O. Farnsworth ,  Michael Z. Felske ,  Pamela S. Gillis ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St. Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

发明人： Leonard O. Farnsworth ,  Michael Z. Felske ,  Pamela S. Gillis ,  Benjamin P. Lynch ,  Michael R. Ouellette ,  Thomas St. Pierre ,  Tad J. Wilder ,  Carl F. Barnhart

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318558 ,  G01R31/318505 ,  G01R31/318516 ,  G11C2029/1208 ,  G11C2029/3202

摘要： An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

摘要翻译： 集成电路的测试和修复的集成电路和方法。 集成电路包括：具有相同功能的多个宏电路; 保险丝库，保险丝的状态存储测试数据，至少指示哪些宏观电路未通过测试; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏 具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的保险丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

公开(公告)号：US08381050B2

公开(公告)日：2013-02-19

申请号：US12625703

申请日：2009-11-25

申请人： Pamela S. Gillis ,  Jack R. Smith ,  Tad J. Wilder ,  Francis Woytowich ,  Tian Xia

发明人： Pamela S. Gillis ,  Jack R. Smith ,  Tad J. Wilder ,  Francis Woytowich ,  Tian Xia

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F1/10 ,  G01R31/318544 ,  G01R31/318552 ,  G01R31/318594

摘要： The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.

摘要翻译： 本文公开的发明提供了延迟和转换故障测试的增加的有效性。 延迟故障测试集成电路的方法包括创建多个测试时钟门控组的步骤。 多个测试时钟门控组包括限定集成电路内的元件间信号路径的元件。 多个测试时钟选通组中的每个元件共享时钟频率和额外的共享特性。 基于测试时钟选通组的成员资格，至少一个测试信号通过至少一个低速栅极晶体管被共同且选择性地连接到包括多个测试时钟门控组中的每一个的每个元件。 为了相同的目的，本发明也可以使用扫描启用门控组来实现。

公开(公告)号：US20110121838A1

公开(公告)日：2011-05-26

申请号：US12625703

申请日：2009-11-25

申请人： Pamela S. Gillis ,  Jack R. Smith ,  Tad J. Wilder ,  Francis Woytowich ,  Tian Xia

发明人： Pamela S. Gillis ,  Jack R. Smith ,  Tad J. Wilder ,  Francis Woytowich ,  Tian Xia

IPC分类号： G01R31/02 ,  G06F1/04

CPC分类号： G06F1/10 ,  G01R31/318544 ,  G01R31/318552 ,  G01R31/318594

摘要： The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.

摘要翻译： 本文公开的发明提供了延迟和转换故障测试的增加的有效性。 延迟故障测试集成电路的方法包括创建多个测试时钟门控组的步骤。 多个测试时钟门控组包括限定集成电路内的元件间信号路径的元件。 多个测试时钟选通组中的每个元件共享时钟频率和额外的共享特性。 基于测试时钟选通组的成员资格，至少一个测试信号通过至少一个低速栅极晶体管被共同且选择性地连接到包括多个测试时钟门控组中的每一个的每个元件。 为了相同的目的，本发明也可以使用扫描启用门控组来实现。

公开(公告)号：US09157956B2

公开(公告)日：2015-10-13

申请号：US13614564

申请日：2012-09-13

申请人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

发明人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

IPC分类号： G06F17/50 ,  G01R31/317 ,  G01R31/30

CPC分类号： G01R31/31718 ,  G01R31/3008

摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非瞬时存储介质存储电压仓的边界作为速度分组测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

公开(公告)号：US20130041608A1

公开(公告)日：2013-02-14

申请号：US13204812

申请日：2011-08-08

申请人： Margaret R. Charlebois ,  Rashmi D. Chatty ,  Christopher D. Hanudel ,  Robert D. Herzl ,  David W. Milton ,  Clarence R. Ogilvie ,  Matthew P. Szafir ,  Tad J. Wilder

发明人： Margaret R. Charlebois ,  Rashmi D. Chatty ,  Christopher D. Hanudel ,  Robert D. Herzl ,  David W. Milton ,  Clarence R. Ogilvie ,  Matthew P. Szafir ,  Tad J. Wilder

IPC分类号： G06F19/00

CPC分类号： G06F17/5031

摘要： Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.

摘要翻译： 本发明的实施例提供了用于预测关键路径的延迟的方法，系统和程序产品。 在一个实施例中，本发明提供了一种预测集成电路的至少一个关键路径的延迟的方法，所述方法包括：确定所述集成电路上的至少一个环形振荡器的延迟; 以及基于角点条件下的关键路径的分量的延迟，所述至少一个关键路径的有线延迟，所述至少一个环形振荡器的延迟在一个 并且确定所述至少一个环形振荡器的延迟。

公开(公告)号：US08302063B2

公开(公告)日：2012-10-30

申请号：US12782359

申请日：2010-05-18

申请人： Jeanne P. Bickford ,  Umberto Garofano ,  James E. Jasmin ,  Ivan L. Wemple ,  Tad J. Wilder

发明人： Jeanne P. Bickford ,  Umberto Garofano ,  James E. Jasmin ,  Ivan L. Wemple ,  Tad J. Wilder

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/08 ,  G06F2217/82

摘要： A method of integrated circuit design and, more particularly, a method and system to optimize semiconductor products for power, performance, noise, die area, and cost through use of variable power supply voltage compression. The method is implemented in a computer-based tool and includes: embedding relationships in an optimization tool running on a computing device, wherein the relationships are based at least partly on performance, power-supply noise, die area, and power; inputting a set of product data and a set of technology data in the optimization tool running on the computing device; and determining product design parameters including power supply voltage, switching-noise-induced power supply voltage variation, and decap area. The determining is based on the relationships, the product data, and the technology data and is performed using the computing device running the optimization tool.

摘要翻译： 一种集成电路设计的方法，更具体地，通过使用可变电源电压压缩来优化用于功率，性能，噪声，管芯面积和成本的半导体产品的方法和系统。 该方法在基于计算机的工具中实现，并且包括：将关系嵌入到在计算设备上运行的优化工具中，其中所述关系至少部分地基于性能，电源噪声，管芯面积和功率; 在计算设备上运行的优化工具中输入一组产品数据和一组技术数据; 并确定产品设计参数，包括电源电压，开关噪声感应电源电压变化和开关区域。 该确定基于关系，产品数据和技术数据，并且使用运行优化工具的计算设备来执行。

公开(公告)号：US20090183135A1

公开(公告)日：2009-07-16

申请号：US12014240

申请日：2008-01-15

申请人： Robert D. Herzl ,  Robert S. Horton ,  Kenneth A. Lauricella ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Nitin Sharma ,  Tad J. Wilder ,  Charles B. Winn

发明人： Robert D. Herzl ,  Robert S. Horton ,  Kenneth A. Lauricella ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Nitin Sharma ,  Tad J. Wilder ,  Charles B. Winn

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).

摘要翻译： 芯片设计方法。 该方法包括识别工程可变逻辑，并用灵活的逻辑块（FLB）替换所识别的工程可变逻辑。