公开(公告)号：US20070189248A1

公开(公告)日：2007-08-16

申请号：US11353886

申请日：2006-02-14

申请人： Li Chang ,  Mark Hahm ,  Simon Baker

发明人： Li Chang ,  Mark Hahm ,  Simon Baker

IPC分类号： H04Q7/24

CPC分类号： H04L1/0071 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/0075 ,  H04L1/08 ,  H04L1/1812 ,  H04L1/1845 ,  H04L2001/0093

摘要： Methods and systems for processing signals in a communication system are disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while simultaneously storing on-chip, a portion of the plurality of information bits in the received bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and the storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits may be partitioned into a functional data processing path and a functional address processing path.

摘要翻译： 公开了用于在通信系统中处理信号的方法和系统，并且可以包括在单个芯片内接收的HSDPA比特流的流水线处理。 流水线可以包括计算接收的HSDPA比特流中的多个信息比特的当前部分的存储器地址，同时在片上存储接收到的当前部分之后的接收比特流中的多个信息比特的一部分 。 可以在计算和存储期间对接收到的HSDPA比特流中当前部分之前的多个信息比特的一部分进行解码。 可以在不使用缓冲器的情况下实现多个信息比特的当前部分的存储器地址的计算。 多个信息位的处理可以被划分为功能数据处理路径和功能地址处理路径。

公开(公告)号：US08036239B2

公开(公告)日：2011-10-11

申请号：US12709871

申请日：2010-02-22

申请人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

发明人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L1/0071 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/0075 ,  H04L1/08 ,  H04L1/1812 ,  H04L1/1845 ,  H04L2001/0093

摘要： A method for processing signals in a communication system is disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while storing on-chip, a portion of the plurality of information bits in the received HSDPA bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits in the received HSDPA bitstream may be partitioned into a functional data processing path and functional address processing path.

摘要翻译： 公开了一种用于在通信系统中处理信号的方法，并且可以包括在单个芯片内接收的HSDPA比特流的流水线处理。 流水线可以包括计算接收的HSDPA比特流中的多个信息比特的当前部分的存储器地址，同时在片上存储在当前部分之后的所接收的HSDPA比特流中的多个信息比特的一部分 。 在计算和存储期间，在当前部分之前的接收的HSDPA比特流中的多个信息比特的一部分可以被解码。 可以在不使用缓冲器的情况下实现多个信息比特的当前部分的存储器地址的计算。 可以将所接收的HSDPA比特流中的多个信息比特的处理划分为功能数据处理路径和功能地址处理路径。

公开(公告)号：US07668188B2

公开(公告)日：2010-02-23

申请号：US11353886

申请日：2006-02-14

申请人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

发明人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L1/0071 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/0075 ,  H04L1/08 ,  H04L1/1812 ,  H04L1/1845 ,  H04L2001/0093

摘要： Methods and systems for processing signals in a communication system are disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while simultaneously storing on-chip, a portion of the plurality of information bits in the received bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and the storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits may be partitioned into a functional data processing path and a functional address processing path.

摘要翻译： 公开了用于在通信系统中处理信号的方法和系统，并且可以包括在单个芯片内接收的HSDPA比特流的流水线处理。 流水线可以包括计算接收的HSDPA比特流中的多个信息比特的当前部分的存储器地址，同时在片上存储接收到的当前部分之后的接收比特流中的多个信息比特的一部分 。 可以在计算和存储期间对接收到的HSDPA比特流中当前部分之前的多个信息比特的一部分进行解码。 可以在不使用缓冲器的情况下实现多个信息比特的当前部分的存储器地址的计算。 多个信息位的处理可以被划分为功能数据处理路径和功能地址处理路径。

公开(公告)号：US20100150165A1

公开(公告)日：2010-06-17

申请号：US12709871

申请日：2010-02-22

申请人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

发明人： Li Fung Chang ,  Mark Hahm ,  Simon Baker

IPC分类号： H04L12/56

CPC分类号： H04L1/0071 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/0075 ,  H04L1/08 ,  H04L1/1812 ,  H04L1/1845 ,  H04L2001/0093

摘要： A method for processing signals in a communication system is disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while storing on-chip, a portion of the plurality of information bits in the received HSDPA bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits in the received HSDPA bitstream may be partitioned into a functional data processing path and functional address processing path.

摘要翻译： 公开了一种用于在通信系统中处理信号的方法，并且可以包括在单个芯片内接收的HSDPA比特流的流水线处理。 流水线可以包括计算接收的HSDPA比特流中的多个信息比特的当前部分的存储器地址，同时在片上存储在当前部分之后的所接收的HSDPA比特流中的多个信息比特的一部分 。 在计算和存储期间，在当前部分之前的接收的HSDPA比特流中的多个信息比特的一部分可以被解码。 可以在不使用缓冲器的情况下实现多个信息比特的当前部分的存储器地址的计算。 可以将所接收的HSDPA比特流中的多个信息比特的处理划分为功能数据处理路径和功能地址处理路径。

公开(公告)号：US20050281331A1

公开(公告)日：2005-12-22

申请号：US10890865

申请日：2004-07-14

申请人： Mark Hahm ,  Li Chang

发明人： Mark Hahm ,  Li Chang

IPC分类号： H04B1/66 ,  H04N7/12 ,  H04N7/26 ,  H04N7/30 ,  H04N11/02 ,  H04N11/04

CPC分类号： H04N19/00096 ,  H04N19/12 ,  H04N19/122 ,  H04N19/126 ,  H04N19/159 ,  H04N19/186 ,  H04N19/42 ,  H04N19/60

摘要： In a video processing system, a method and system for dynamically configurable DCT/IDCT module in a wireless handset are provided. A processor may be used to configure a quantization scheme and video format mode of operation and to configure a processing network in a DCT/IDCT module. The mode of operation may depend on whether the received video signal is in JPEG, MPEG, and/or H.263 format. The processing network may be configured into a DCT processing network configuration or an IDCT processing network configuration based on whether the received video signal is to be encoded or decoded respectively. The DCT/IDCT module may comprise a FIFO, an adder/subtractor, a multipler/accumulator, a plurality of digital dividers, and a de-quantizer. The plurality of digital dividers may comprise a 12-bit divider and an 7-bit divider. The mode and configuration modifications may be dynamically performed during operation of the wireless handset.

摘要翻译： 在视频处理系统中，提供了一种在无线手机中用于动态配置的DCT / IDCT模块的方法和系统。 处理器可以用于配置量化方案和视频格式操作模式，并且在DCT / IDCT模块中配置处理网络。 操作模式可以取决于所接收的视频信号是JPEG，MPEG和/或H.263格式。 处理网络可以被配置为DCT处理网络配置或IDCT处理网络配置，基于所接收的视频信号是否被分别编码或解码。 DCT / IDCT模块可以包括FIFO，加法器/减法器，乘法器/累加器，多个数字分频器和去量化器。 多个数字分频器可以包括12位分频器和7位分频器。 可以在无线手机的操作期间动态地执行模式和配置修改。

公开(公告)号：US20070025428A1

公开(公告)日：2007-02-01

申请号：US11221145

申请日：2005-09-06

申请人： Mark Hahm ,  Li Chang ,  Nelson Sollenberger

发明人： Mark Hahm ,  Li Chang ,  Nelson Sollenberger

IPC分类号： H04B1/707

CPC分类号： H04B1/70735 ,  H04B1/7083 ,  H04B2201/70707

摘要： A baseband processing module includes TX processing components, a processor, memory, an RX interface, and a cell searcher module. The TX processing components receive outbound data, process the outbound data to produce a baseband TX signal, and output the baseband TX signal to a RF front end of the RF transceiver. The RX interface receives a baseband RX signal from the RF front end carrying a WCDMA signal. The cell searcher module receives the baseband RX signal, scans for WCDMA energy within the baseband RX signal, acquires slot synchronization to the WCDMA signal based upon correlation with a Primary Synchronization Channel (PSCH) of the WCDMA signal, acquires frame synchronization to, and identify a code group of, the WCDMA signal based upon correlation with a Secondary Synchronization Channel (SSCH) of the WCDMA signal, and identifies the scrambling code of the WCDMA signal based upon correlation with a Common Pilot Channel (CPICH) of the WCDMA signal.

摘要翻译： 基带处理模块包括TX处理组件，处理器，存储器，RX接口和小区搜索器模块。 TX处理组件接收出站数据，处理出站数据以产生基带TX信号，并将基带TX信号输出到RF收发器的RF前端。 RX接口从承载WCDMA信号的RF前端接收基带RX信号。 小区搜索器模块接收基带RX信号，扫描基带RX信号内的WCDMA能量，基于与WCDMA信号的主同步信道（PSCH）的相关性，获取WCDMA信号的时隙同步，获取帧同步和识别 基于与WCDMA信号的次同步信道（SSCH）的相关性的WCDMA信号的码组，并且基于与WCDMA信号的公共导频信道（CPICH）的相关性来识别WCDMA信号的扰码。

公开(公告)号：US20060270369A1

公开(公告)日：2006-11-30

申请号：US11141478

申请日：2005-05-31

申请人： Mark Hahm ,  Li Chang

发明人： Mark Hahm ,  Li Chang

IPC分类号： H04B1/00

CPC分类号： H03M13/658 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/23 ,  H03M13/2975 ,  H03M13/3922 ,  H03M13/6306 ,  H03M13/6362 ,  H04L1/0051 ,  H04L1/0054 ,  H04L1/0066 ,  H04L1/1819 ,  H04L1/1845

摘要： A baseband processing module for use within a Radio Frequency (RF) transceiver includes a downlink/uplink interface, TX processing components, a processor, memory, RX processing components, and a turbo decoding module. The RX processing components receive a baseband RX signal from the RF front end, produce a set of IR samples from the baseband RX signal, and transfer the set of IR samples to the memory. The turbo decoding module receives a set of IR samples from the memory, forms a turbo code word from the set of IR samples, turbo decodes the turbo code word to produce inbound data, and outputs the inbound data to the downlink/uplink interface. The turbo decoding module performs metric normalization based upon a chosen metric, performs de-rate matching on the set of IR samples, performs error detection operations, and extracts information from a MAC packet that it produces.

摘要翻译： 用于射频（RF）收发器的基带处理模块包括下行链路/上行链路接口，TX处理组件，处理器，存储器，RX处理组件和turbo解码模块。 RX处理组件从RF前端接收基带RX信号，从基带RX信号产生一组IR样本，并将该组IR样本传送到存储器。 turbo解码模块从存储器接收一组IR样本，从该IR样本组中形成turbo码字，对turbo码字进行turbo解码以产生入站数据，并将入站数据输出到下行链路/上行链路接口。 turbo解码模块基于所选择的度量来执行度量标准化，对所述IR样本集执行去速率匹配，执行错误检测操作，以及从其产生的MAC分组中提取信息。

公开(公告)号：US20070192393A1

公开(公告)日：2007-08-16

申请号：US11353367

申请日：2006-02-14

申请人： Taiyi Cheng ,  Mark Hahm ,  Li Chang

发明人： Taiyi Cheng ,  Mark Hahm ,  Li Chang

IPC分类号： G06F17/14

CPC分类号： G06F17/147 ,  H04N19/42 ,  H04N19/60

摘要： Certain aspects of a method and system for hardware and software shareable DCT/IDCT control interface are provided. A single DCT/IDCT interface may be utilized to provide hardware or software control of a DCT/IDCT module. During hardware control the DCT/IDCT module may be utilized for JPEG compression, for example. During software control a CPU may utilize the DCT/IDCT module for audio, software, and/or video applications, for example. The interface may enable selecting a quantization table for use by the DCT/IDCT module. The interface may also enable selecting encoding or decoding operations to be performed by the DCT/IDCT module. The interface may also enable toggling between a first and a second portion of a data buffer utilized by the DCT/IDCT module. Moreover, the interface may enable starting processing of a data block by the DCT/IDCT module and indicating when the DCT/IDCT module has completed processing the data block.

摘要翻译： 提供了硬件和软件可共享的DCT / IDCT控制接口的方法和系统的某些方面。 可以使用单个DCT / IDCT接口来提供DCT / IDCT模块的硬件或软件控制。 在硬件控制期间，DCT / IDCT模块可以用于例如JPEG压缩。 在软件控制期间，例如，CPU可以将DCT / IDCT模块用于音频，软件和/或视频应用。 该接口可以使得能够选择用于DCT / IDCT模块的量化表。 该接口还可以使得能够选择要由DCT / IDCT模块执行的编码或解码操作。 接口还可以使得能够切换由DCT / IDCT模块使用的数据缓冲器的第一和第二部分。 此外，该接口可以使DCT / IDCT模块能够开始处理数据块，并且指示DCT / IDCT模块何时完成数据块的处理。

公开(公告)号：US20070189614A1

公开(公告)日：2007-08-16

申请号：US11353528

申请日：2006-02-14

申请人： Taiyi Cheng ,  Mark Hahm ,  Li Chang

发明人： Taiyi Cheng ,  Mark Hahm ,  Li Chang

IPC分类号： G06K9/36

CPC分类号： H04N19/42

摘要： A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data

摘要翻译： 描述了集成嵌入式图像和视频加速器中流水线处理的方法和系统。 在集成嵌入式图像和视频加速器中用于流水线处理的系统的方面可以包括能够对单个芯片内的视频数据进行流水线处理的电路，其中流水线处理还可以包括对视频数据块进行解码，同时对先前 解码的视频数据块。 系统的方面还可以包括能够在单个芯片内转换所述视频数据的块的电路，同时在所述单个芯片内同时对先前变换的视频数据块进行编码

公开(公告)号：US20060274715A1

公开(公告)日：2006-12-07

申请号：US11142213

申请日：2005-06-01

申请人： Mark Hahm ,  Li Chang ,  Michiel Lotter

发明人： Mark Hahm ,  Li Chang ,  Michiel Lotter

IPC分类号： H04J3/24

CPC分类号： H04L1/0051 ,  H04L1/0054 ,  H04L1/0066 ,  H04L1/1819 ,  H04L1/1845

摘要： A baseband processing module for use within a Radio Frequency (RF) transceiver includes a downlink/uplink interface, TX processing components, a processor, memory, RX processing components, and a turbo decoding module. The RX processing components receive a baseband RX signal from the RF front end, produce a set of IR samples from the baseband RX signal, and transfer the set of IR samples to the memory. The turbo decoding module receives at least one set of IR samples from the memory, forms a turbo code word from the at least one set of IR samples, turbo decodes the turbo code word to produce inbound data, and outputs the inbound data to the downlink/uplink interface. The turbo decoding module performs metric normalization based upon a chosen metric, performs de-rate matching, performs error detection operations, and extracts information from a MAC packet that it produces.