公开(公告)号：US5872063A

公开(公告)日：1999-02-16

申请号：US5568

申请日：1998-01-12

申请人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

发明人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/70

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  Y10S257/90

摘要： A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

摘要翻译： 描述了自对准结构和蚀刻自对准结构中的接触孔的方法。 选择介电材料，蚀刻方法和蚀刻剂以提供高选择性蚀刻。 该结构包括在电极和盖的侧壁上具有氮氧化硅帽和氮氧化硅间隔物的电极。 氮化硅的蚀刻停止层沉积在覆盖间隔物和盖的衬底上。 氧化硅层沉积在蚀刻停止层上。 使用蚀刻方法和蚀刻剂，其提供氧化硅的蚀刻速率与氮化硅或氮氧化硅的蚀刻速率的比率至少为8，氮化硅的蚀刻速率与硅氧化物的蚀刻速率的比率 至少两个。

公开(公告)号：US06172411B2

公开(公告)日：2001-01-09

申请号：US09208921

申请日：1998-12-10

申请人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

发明人： Li-chih Chao ,  Jhon-Jhy Liaw ,  Yuan-Chang Huang ,  Jin-Yuan Lee

IPC分类号： H01L27088

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  Y10S257/90

摘要： A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

摘要翻译： 描述了自对准结构和蚀刻自对准结构中的接触孔的方法。 选择介电材料，蚀刻方法和蚀刻剂以提供高选择性蚀刻。 该结构包括在电极和盖的侧壁上具有氮氧化硅帽和氮氧化硅间隔物的电极。 氮化硅的蚀刻停止层沉积在覆盖间隔物和盖的衬底上。 氧化硅层沉积在蚀刻停止层上。 使用蚀刻方法和蚀刻剂，其提供氧化硅的蚀刻速率与氮化硅或氮氧化硅的蚀刻速率的比率至少为8，氮化硅的蚀刻速率与硅氧化物的蚀刻速率的比率 至少两个。

公开(公告)号：US06211061B1

公开(公告)日：2001-04-03

申请号：US09431536

申请日：1999-10-29

申请人： Chao-Cheng Chen ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Li-chih Chao ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Li-chih Chao ,  Chia-Shiung Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： A method for forming a dual damascene structure in a carbon-based, low-K material. The process begins by providing a semiconductor structure having a first metal pattern thereover, wherein the first metal pattern has a first barrier layer thereon. An organic dielectric layer is formed on the first barrier layer, and a hard mask layer is formed on the dielectric layer. The hard mask layer and the dielectric layer are patterned to form a trench. A second barrier layer is formed over the hard mask layer and on the bottom and sidewalls of the trench. A barc layer is formed over the second barrier layer, thereby filling the trench. The barc layer, the second barrier layer, and the dielectric layer are patterned to form a via opening, preferably using a photoresist mask. The barc layer is patterned without faceting the edges of the via opening due to the second barrier layer. The barc layer and the etch mask are removed by the dielectric layer etch. The first barrier layer and the second barrier layer are removed. A third barrier layer is formed on the bottom and sidewalls of the trench, on the sidewalls of the via opening, and on the first metal pattern through the via opening. The trench and the via opening are filled with metal to form a damascene structure.

摘要翻译： 一种在碳基低K材料中形成双镶嵌结构的方法。 该过程开始于提供其上具有第一金属图案的半导体结构，其中第一金属图案在其上具有第一阻挡层。 在第一阻挡层上形成有机电介质层，在电介质层上形成硬掩模层。 图案化硬掩模层和电介质层以形成沟槽。 第二阻挡层形成在硬掩模层之上以及沟槽的底部和侧壁上。 在第二阻挡层上形成棒状层，由此填充沟槽。 将棒状层，第二阻挡层和电介质层图案化以形成通孔，优选使用光致抗蚀剂掩模。 由于第二阻挡层，棒状层被图案化而不使通孔开口的边缘刻划。 通过电介质层蚀刻去除棒状层和蚀刻掩模。 去除第一阻挡层和第二阻挡层。 第三阻挡层形成在沟槽的底部和侧壁上，通孔开口的侧壁上，通过通孔开口形成在第一金属图案上。 沟槽和通孔开口用金属填充以形成镶嵌结构。