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    Strained silicon layer fabrication with reduced dislocation defect density
    1.
    发明授权
    Strained silicon layer fabrication with reduced dislocation defect density 有权
    应变硅层制造具有减少的位错缺陷密度

    公开(公告)号：US07105393B2

    公开(公告)日：2006-09-12

    申请号：US10769316

    申请日：2004-01-30

    申请人： Liang-Gi Yao ,  Tien-Chih Chang ,  CC Lin ,  Shin-Chang Chen ,  Mong-Song Liang

    发明人： Liang-Gi Yao ,  Tien-Chih Chang ,  CC Lin ,  Shin-Chang Chen ,  Mong-Song Liang

    IPC分类号： H01L21/338

    CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532

    摘要： A strained silicon layer fabrication employs a substrate having successively formed thereover: (1) a first silicon-germanium alloy material layer; (2) a first silicon layer; (3) a second silicon-germanium alloy material layer; and (4) a second silicon layer. Within the fabrication each of the first silicon-germanium alloy layer and the second silicon-germanium alloy layer is formed of a thickness less than a threshold thickness for dislocation defect formation, such as to provide attenuated dislocation defect formation within the strained silicon layer fabrication.

    摘要翻译： 应变硅层制造采用在其上依次形成的基板：（1）第一硅 - 锗合金材料层; （2）第一硅层; （3）第二硅 - 锗合金材料层; 和（4）第二硅层。 在制造中，第一硅 - 锗合金层和第二硅 - 锗合金层中的每一个由低于用于位错缺陷形成的阈值厚度的厚度形成，例如在应变硅层制造中提供衰减的位错缺陷形成。

    Strained silicon layer fabrication with reduced dislocation defect density
    2.
    发明申请
    Strained silicon layer fabrication with reduced dislocation defect density 有权
    应变硅层制造具有减少的位错缺陷密度

    公开(公告)号：US20050170577A1

    公开(公告)日：2005-08-04

    申请号：US10769316

    申请日：2004-01-30

    申请人： Liang-Gi Yao ,  Tien-Chih Chang ,  CC Lin ,  Shin-Chang Chen ,  Mong-Song Liang

    发明人： Liang-Gi Yao ,  Tien-Chih Chang ,  CC Lin ,  Shin-Chang Chen ,  Mong-Song Liang

    IPC分类号： C30B1/00 ,  H01L21/20 ,  H01L21/338

    CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532

    摘要： A strained silicon layer fabrication employs a substrate having successively formed thereover: (1) a first silicon-germanium alloy material layer; (2) a first silicon layer; (3) a second silicon-germanium alloy material layer; and (4) a second silicon layer. Within the fabrication each of the first silicon-germanium alloy layer and the second silicon-germanium alloy layer is formed of a thickness less than a threshold thickness for dislocation defect formation, such as to provide attenuated dislocation defect formation within the strained silicon layer fabrication.

    摘要翻译： 应变硅层制造采用在其上依次形成的基板：（1）第一硅 - 锗合金材料层; （2）第一硅层; （3）第二硅 - 锗合金材料层; 和（4）第二硅层。 在制造中，第一硅 - 锗合金层和第二硅 - 锗合金层中的每一个由低于用于位错缺陷形成的阈值厚度的厚度形成，例如在应变硅层制造中提供衰减的位错缺陷形成。

    Noble high-k device
    5.
    发明授权
    Noble high-k device 有权
    高贵的高k设备

    公开(公告)号：US07351994B2

    公开(公告)日：2008-04-01

    申请号：US10762164

    申请日：2004-01-21

    申请人： Liang-Gi Yao ,  Tien-Chih Chang ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

    发明人： Liang-Gi Yao ,  Tien-Chih Chang ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

    IPC分类号： H01L29/06 ,  H01L21/336

    CPC分类号： H01L29/517 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

    摘要： At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one dielectric gate oxide portion over the strained substrate. The at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0. A device over each of the at least one dielectric gate oxide portion to complete the least one high-k device. A method of forming the at least one high-k device.

    摘要翻译： 至少一个高k装置和用于形成至少一个高k装置的方法包括以下。 具有在其上形成的应变衬底的结构。 应变衬底包括至少最上层的应变Si外延层。 在应变衬底上的至少一个电介质栅极氧化物部分。 所述至少一个电介质栅极氧化物部分具有大于约4.0的介电常数。 在所述至少一个电介质栅极氧化物部分中的每一个上方的器件，以完成所述至少一个高k器件。 一种形成所述至少一个高k装置的方法。

    Noble high-k device
    8.
    发明申请
    Noble high-k device 有权
    高贵的高k设备

    公开(公告)号：US20050156255A1

    公开(公告)日：2005-07-21

    申请号：US10762164

    申请日：2004-01-21

    申请人： Liang-Gi Yao ,  Tien-Chih Chang ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

    发明人： Liang-Gi Yao ,  Tien-Chih Chang ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

    IPC分类号： H01L21/8238 ,  H01L29/10 ,  H01L29/51 ,  H01L21/336 ,  H01L31/072

    CPC分类号： H01L29/517 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

    摘要： At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one dielectric gate oxide portion over the strained substrate. The at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0. A device over each of the at least one dielectric gate oxide portion to complete the least one high-k device. A method of forming the at least one high-k device.

    摘要翻译： 至少一个高k装置和用于形成至少一个高k装置的方法包括以下。 具有在其上形成的应变衬底的结构。 应变衬底包括至少最上层的应变Si外延层。 在应变衬底上的至少一个电介质栅极氧化物部分。 所述至少一个电介质栅极氧化物部分具有大于约4.0的介电常数。 在所述至少一个电介质栅极氧化物部分中的每一个上方的器件，以完成所述至少一个高k器件。 一种形成所述至少一个高k装置的方法。

    Relaxed silicon germanium substrate with low defect density
    9.
    发明授权
    Relaxed silicon germanium substrate with low defect density 有权
    具有低缺陷密度的松弛硅锗衬底

    公开(公告)号：US06878610B1

    公开(公告)日：2005-04-12

    申请号：US10228545

    申请日：2002-08-27

    申请人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

    发明人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

    IPC分类号： C30B1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/36 ,  H01L21/84 ,  H01L29/10

    CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/324

    摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe, has been developed. In a first embodiment of this invention the relaxed, low density SiGe layer is epitaxially grown on an silicon layer which in turn is located on an underlying SiGe layer. During the epitaxial growth of the overlying SiGe layer defects are formed in the underlying silicon layer resulting in the desired, relaxation, and decreased defect density for the SiGe layer. A second embodiment features an anneal procedure performed during growth of the relaxed SiGe layer, resulting in additional relaxation and decreased defect density, while a third embodiment features an anneal procedure performed to the underlying silicon layer prior to epitaxial growth of the relaxed SiGe layer, again allowing optimized relaxation and defect density to be realized for the SiGe layer. The ability to obtain a strained silicon layer on a relaxed, low defect density SiGe layer, allows devices with enhanced carrier mobility to be formed in the surface of the strained silicon layer, with decreased risk of leakage due the presence of the underlying, relaxed, low defect density SiGe layer.

    摘要翻译： 已经开发了在松弛的低缺陷密度半导体合金层如SiGe上形成应变硅层的方法。 在本发明的第一实施例中，松散的低密度SiGe层在硅层上外延生长，硅层又位于下面的SiGe层上。 在覆盖SiGe层的外延生长期间，在下层硅层中形成缺陷，导致SiGe层所需的，松弛的和降低的缺陷密度。 第二个实施例的特征在于在松弛的SiGe层的生长期间执行的退火程序，导致附加的松弛和降低的缺陷密度，而第三实施例的特征在于在弛豫的SiGe层的外延生长之前对下面的硅层进行退火处理 允许为SiGe层实现优化的弛豫和缺陷密度。 在松弛的低缺陷密度SiGe层上获得应变硅层的能力允许在应变硅层的表面形成具有增强的载流子迁移率的器件，由于存在下面的，放松的， 低缺陷密度SiGe层。