Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited
    1.
    发明授权
    Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited 有权
    指示当冻结位设置和上下文切换禁止时管道资源稳定状态的确认

    公开(公告)号:US07467289B1

    公开(公告)日:2008-12-16

    申请号:US11553913

    申请日:2006-10-27

    IPC分类号: G06F11/30

    CPC分类号: G06F9/485

    摘要: Software can freeze portions of a pipeline operation in a processor by asserting a predetermined freeze register in the processor. The processor halts operations relating to portions of a common pipeline processing in response to an asserted freeze register. Processor resources that operate downstream from the common pipeline continue to process any scheduled instructions. The processor is prevented from initiating any context switching in which a processor resource is allocated to a different channel. The processor stops supplying any additional data to downstream resources and ensures that the interface to downstream resources is clear of previously sent data. The processor prevents state machines from making additional requests. The processor asserts an acknowledgement indication in response to the freeze assertion when the processing has reached a stable state. Software is allowed to manipulate states and registers within the processor. Clearing the freeze register allows processing to resume.

    摘要翻译: 软件可以通过在处理器中断言预定的冻结寄存器来冻结处理器中流水线操作的部分。 响应于断言的冻结寄存器,处理器停止与公共流水线处理的部分有关的操作。 在公共管道下游运行的处理器资源继续处理任何计划的指令。 防止处理器发起其中将处理器资源分配给不同信道的任何上下文切换。 处理器停止向下游资源提供任何附加数据,并确保与下游资源的接口清除以前发送的数据。 处理器可防止状态机发出其他请求。 当处理已经达到稳定状态时,处理器响应于冻结断言声明确认指示。 允许软件在处理器内操纵状态和寄存器。 清除冻结寄存器允许处理恢复。

    Method and apparatus for context switching of multiple engines
    2.
    发明授权
    Method and apparatus for context switching of multiple engines 有权
    多台发动机上下文切换的方法和装置

    公开(公告)号:US08108879B1

    公开(公告)日:2012-01-31

    申请号:US11553901

    申请日:2006-10-27

    IPC分类号: G06F9/46

    CPC分类号: G06F9/52

    摘要: A processor having multiple independent engines can concurrently support a number of independent processes or operation contexts. The processor can independently schedule instructions for execution by the engines. The processor can independently switch the operation context that an engine supports. The processor can maintain the integrity of the operations performed and data processed by each engine during a context switch by controlling the manner in which the engine transitions from one operation context to the next. The processor can wait for the engine to complete processing of pipelined instructions of a first context before switching to another context, or the processor can halt the operation of the engine in the midst of one or more instructions to allow the engine to execute instructions corresponding to another context. The processor can affirmatively verify completion of tasks for a specific operation context.

    摘要翻译: 具有多个独立引擎的处理器可以同时支持多个独立的进程或操作上下文。 处理器可以独立地调度指令以供引擎执行。 处理器可以独立地切换引擎支持的操作上下文。 处理器可以通过控制引擎从一个操作上下文转换到下一个操作上下文的方式来保持在上下文切换期间由每个引擎执行的操作和数据处理的完整性。 处理器可以等待引擎在切换到另一个上下文之前完成对第一上下文的流水线指令的处理,或者处理器可以在一个或多个指令中停止发动机的操作,以允许引擎执行对应于 另一个上下文。 处理器可以肯定地验证特定操作上下文的任务完成。

    Apparatus and method for servicing multiple graphics processing channels
    3.
    发明授权
    Apparatus and method for servicing multiple graphics processing channels 有权
    用于维护多个图形处理通道的装置和方法

    公开(公告)号:US08031198B1

    公开(公告)日:2011-10-04

    申请号:US11555078

    申请日:2006-10-31

    IPC分类号: G06F15/00 G06T1/00 G06T15/00

    CPC分类号: G06T1/20

    摘要: An apparatus and method for servicing multiple graphics processing channels are described. In one embodiment, a graphics processing apparatus includes a scheduler configured to direct servicing of a graphics processing channel by issuing an index related to the graphics processing channel. The graphics processing apparatus also includes a processing core connected to the scheduler. The processing core is configured to service the graphics processing channel by: (i) correlating the index with a memory location at which an instance block for the graphics processing channel is stored; and (ii) accessing the instance block stored at the memory location.

    摘要翻译: 描述了一种用于维护多个图形处理通道的装置和方法。 在一个实施例中,图形处理装置包括调度器,被配置为通过发布与图形处理通道相关的索引来直接对图形处理通道进行服务。 图形处理装置还包括连接到调度器的处理核心。 处理核心被配置为通过以下操作来服务图形处理通道:(i)将索引与存储图形处理通道的实例块的存储器位置相关联; 和(ii)访问存储在存储器位置的实例块。

    Asynchronous interface for communicating between clock domains
    4.
    发明授权
    Asynchronous interface for communicating between clock domains 有权
    用于在时钟域之间通信的异步接口

    公开(公告)号:US08547993B1

    公开(公告)日:2013-10-01

    申请号:US11463682

    申请日:2006-08-10

    IPC分类号: H04L12/66 H04L29/06

    CPC分类号: H04L29/06 G06F13/4226

    摘要: Methods, apparatuses, and systems are presented for performing asynchronous communications involving using an asynchronous interface to send signals between a source device and a plurality of client devices, the source device and the plurality of client devices being part of a processing unit capable of performing graphics operations, the source device being coupled to the plurality of client devices using the asynchronous interface, wherein the asynchronous interface includes at least one request signal, at least one address signal, at least one acknowledge signal, and at least one data signal, and wherein the asynchronous interface operates in accordance with at least one programmable timing characteristic associated with the source device.

    摘要翻译: 呈现用于执行涉及使用异步接口在源设备和多个客户端设备之间发送信号的异步通信的方法,设备和系统,源设备和多个客户端设备是能够执行图形的处理单元的一部分 所述源设备使用所述异步接口耦合到所述多个客户端设备,其中所述异步接口包括至少一个请求信号,至少一个地址信号,至少一个确认信号和至少一个数据信号,并且其中 异步接口根据与源设备相关联的至少一个可编程定时特性进行操作。

    Shadow unit for shadowing circuit status
    5.
    发明授权
    Shadow unit for shadowing circuit status 有权
    阴影单元用于阴影电路状态

    公开(公告)号:US07937606B1

    公开(公告)日:2011-05-03

    申请号:US11437112

    申请日:2006-05-18

    IPC分类号: G06F1/04 G06F15/177

    摘要: Generally, the present disclosure concerns systems and methods for shadowing status for a circuit with a shadow unit. In one aspect, a system comprises a first circuit in a first dynamic clock domain of a plurality of dynamic clock domains, a processor configured to execute software instructions to generate a request for a status of the first circuit, and a second circuit coupled to the first circuit and to the processor. The second circuit, outside the first dynamic clock domain, is configured to shadow a status of the first circuit and to respond to the request for the status of the first circuit with the shadowed status.

    摘要翻译: 通常,本公开涉及用于具有阴影单元的电路的阴影状态的系统和方法。 在一个方面,系统包括多个动态时钟域的第一动态时钟域中的第一电路,被配置为执行软件指令以产生对第一电路的状态的请求的处理器,以及耦合到 第一电路和处理器。 在第一动态时钟域之外的第二电路被配置为影响第一电路的状态并且响应于具有阴影状态的第一电路的状态的请求。

    Cooperative scheduling for multiple consumers
    6.
    发明授权
    Cooperative scheduling for multiple consumers 有权
    合作调度多个消费者

    公开(公告)号:US07577762B1

    公开(公告)日:2009-08-18

    申请号:US11048386

    申请日:2005-02-01

    IPC分类号: G06F3/00

    CPC分类号: G06F9/4881

    摘要: A system and method schedules command streams for processing by a variety of consumers. A single command stream is parsed and commands included in the command stream are output to one of the variety of consumers at a time. A pre-emptive scheduling mechanism is used so that a first consumer may yield to a second consumer when the first consumer has received a sufficient amount of commands. The pre-emptive scheduling enables several of the consumers to process commands concurrently. The pre-emptive scheduling mechanism may be implemented by a device driver inserting yield commands into the command stream or by a unit parsing the command stream.

    摘要翻译: 系统和方法调度命令流以供各种消费者处理。 解析单个命令流,并将命令流中包含的命令一次输出到各种消费者之一。 使用优先调度机制,使得当第一消费者已经接收到足够量的命令时,第一消费者可以向第二消费者产生收益。 抢占式调度使得几个消费者能够同时处理命令。 预先调度机制可以由设备驱动程序将产出命令插入到命令流中或通过解析命令流的单元来实现。

    Data synchronization with multiple producers
    7.
    发明授权
    Data synchronization with multiple producers 有权
    与多个生产者的数据同步

    公开(公告)号:US07685370B1

    公开(公告)日:2010-03-23

    申请号:US11305781

    申请日:2005-12-16

    IPC分类号: G06F12/00

    CPC分类号: G06F9/544 G06F9/52

    摘要: A data processing system can establish or maintain data coherency by issuing a data flush operation. An agent can initialize a first flush operation by writing to a flush register. The agent can determine that the flush operation is complete by reading a status indicator from a status register. Additional agents can independently issue flush operations during the pendency of the first flush operation. A second flush instruction and any additional flush instructions that issue during the pendency of the first flush operation set a flush pending indicator in a status register. Once the first flush operation completes, the host performs all pending flush operations in a single second flush operation. The status indicator does not indicate a completed flush operation for the first flush operation until all flush operations are complete. Multiple co-pending flush operations are collapsed into at most two flush operations.

    摘要翻译: 数据处理系统可以通过发出数据刷新操作来建立或维护数据一致性。 代理可以通过写入刷新寄存器来初始化第一次刷新操作。 代理可以通过从状态寄存器读取状态指示器来确定刷新操作是否完成。 附加代理可以在第一次刷新操作的后期期间独立地发出刷新操作。 在第一次刷新操作的未决期间发出的第二个刷新指令和任何其他刷新指令将在状态寄存器中设置一个清除挂起指示符。 第一次刷新操作完成后,主机将在单次第二次刷新操作中执行所有挂起的刷新操作。 状态指示器在第一次刷新操作完成之前,并不表示完成刷新操作,直到所有刷新操作完成。 多个共同待处理的刷新操作将折叠到最多两次刷新操作。