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    Apparatus and method for servicing multiple graphics processing channels
    1.
    发明授权
    Apparatus and method for servicing multiple graphics processing channels 有权
    用于维护多个图形处理通道的装置和方法

    公开(公告)号：US08031198B1

    公开(公告)日：2011-10-04

    申请号：US11555078

    申请日：2006-10-31

    申请人： Jeffrey M. Smith ,  Shail Dave ,  Wei-Je Huang ,  Lincoln G. Garlick ,  Paolo E. Sabella

    发明人： Jeffrey M. Smith ,  Shail Dave ,  Wei-Je Huang ,  Lincoln G. Garlick ,  Paolo E. Sabella

    IPC分类号： G06F15/00 ,  G06T1/00 ,  G06T15/00

    CPC分类号： G06T1/20

    摘要： An apparatus and method for servicing multiple graphics processing channels are described. In one embodiment, a graphics processing apparatus includes a scheduler configured to direct servicing of a graphics processing channel by issuing an index related to the graphics processing channel. The graphics processing apparatus also includes a processing core connected to the scheduler. The processing core is configured to service the graphics processing channel by: (i) correlating the index with a memory location at which an instance block for the graphics processing channel is stored; and (ii) accessing the instance block stored at the memory location.

    摘要翻译： 描述了一种用于维护多个图形处理通道的装置和方法。 在一个实施例中，图形处理装置包括调度器，被配置为通过发布与图形处理通道相关的索引来直接对图形处理通道进行服务。 图形处理装置还包括连接到调度器的处理核心。 处理核心被配置为通过以下操作来服务图形处理通道：（i）将索引与存储图形处理通道的实例块的存储器位置相关联; 和（ii）访问存储在存储器位置的实例块。

    Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited
    2.
    发明授权
    Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited 有权
    指示当冻结位设置和上下文切换禁止时管道资源稳定状态的确认

    公开(公告)号：US07467289B1

    公开(公告)日：2008-12-16

    申请号：US11553913

    申请日：2006-10-27

    申请人： Lincoln G. Garlick ,  Vikramjeet Singh ,  David W. Nuechterlein ,  Shail Dave ,  Jeffrey M. Smith ,  Paolo E. Sabella ,  Dennis K. Ma

    发明人： Lincoln G. Garlick ,  Vikramjeet Singh ,  David W. Nuechterlein ,  Shail Dave ,  Jeffrey M. Smith ,  Paolo E. Sabella ,  Dennis K. Ma

    IPC分类号： G06F11/30

    CPC分类号： G06F9/485

    摘要： Software can freeze portions of a pipeline operation in a processor by asserting a predetermined freeze register in the processor. The processor halts operations relating to portions of a common pipeline processing in response to an asserted freeze register. Processor resources that operate downstream from the common pipeline continue to process any scheduled instructions. The processor is prevented from initiating any context switching in which a processor resource is allocated to a different channel. The processor stops supplying any additional data to downstream resources and ensures that the interface to downstream resources is clear of previously sent data. The processor prevents state machines from making additional requests. The processor asserts an acknowledgement indication in response to the freeze assertion when the processing has reached a stable state. Software is allowed to manipulate states and registers within the processor. Clearing the freeze register allows processing to resume.

    摘要翻译： 软件可以通过在处理器中断言预定的冻结寄存器来冻结处理器中流水线操作的部分。 响应于断言的冻结寄存器，处理器停止与公共流水线处理的部分有关的操作。 在公共管道下游运行的处理器资源继续处理任何计划的指令。 防止处理器发起其中将处理器资源分配给不同信道的任何上下文切换。 处理器停止向下游资源提供任何附加数据，并确保与下游资源的接口清除以前发送的数据。 处理器可防止状态机发出其他请求。 当处理已经达到稳定状态时，处理器响应于冻结断言声明确认指示。 允许软件在处理器内操纵状态和寄存器。 清除冻结寄存器允许处理恢复。

    Asynchronous interface for communicating between clock domains
    3.
    发明授权
    Asynchronous interface for communicating between clock domains 有权
    用于在时钟域之间通信的异步接口

    公开(公告)号：US08547993B1

    公开(公告)日：2013-10-01

    申请号：US11463682

    申请日：2006-08-10

    申请人： Lincoln G. Garlick ,  Richard A. Silkebakken ,  Prakash G. Apte ,  Paolo E. Sabella ,  Samuel H. Duncan ,  Dennis K. Ma ,  Sean J. Treichler

    发明人： Lincoln G. Garlick ,  Richard A. Silkebakken ,  Prakash G. Apte ,  Paolo E. Sabella ,  Samuel H. Duncan ,  Dennis K. Ma ,  Sean J. Treichler

    IPC分类号： H04L12/66 ,  H04L29/06

    CPC分类号： H04L29/06 ,  G06F13/4226

    摘要： Methods, apparatuses, and systems are presented for performing asynchronous communications involving using an asynchronous interface to send signals between a source device and a plurality of client devices, the source device and the plurality of client devices being part of a processing unit capable of performing graphics operations, the source device being coupled to the plurality of client devices using the asynchronous interface, wherein the asynchronous interface includes at least one request signal, at least one address signal, at least one acknowledge signal, and at least one data signal, and wherein the asynchronous interface operates in accordance with at least one programmable timing characteristic associated with the source device.

    摘要翻译： 呈现用于执行涉及使用异步接口在源设备和多个客户端设备之间发送信号的异步通信的方法，设备和系统，源设备和多个客户端设备是能够执行图形的处理单元的一部分 所述源设备使用所述异步接口耦合到所述多个客户端设备，其中所述异步接口包括至少一个请求信号，至少一个地址信号，至少一个确认信号和至少一个数据信号，并且其中 异步接口根据与源设备相关联的至少一个可编程定时特性进行操作。

    Method and apparatus for context switching of multiple engines
    4.
    发明授权
    Method and apparatus for context switching of multiple engines 有权
    多台发动机上下文切换的方法和装置

    公开(公告)号：US08108879B1

    公开(公告)日：2012-01-31

    申请号：US11553901

    申请日：2006-10-27

    申请人： Lincoln G. Garlick ,  Dennis K. Ma ,  Paolo E. Sabella ,  David W. Nuechterlein

    发明人： Lincoln G. Garlick ,  Dennis K. Ma ,  Paolo E. Sabella ,  David W. Nuechterlein

    IPC分类号： G06F9/46

    CPC分类号： G06F9/52

    摘要： A processor having multiple independent engines can concurrently support a number of independent processes or operation contexts. The processor can independently schedule instructions for execution by the engines. The processor can independently switch the operation context that an engine supports. The processor can maintain the integrity of the operations performed and data processed by each engine during a context switch by controlling the manner in which the engine transitions from one operation context to the next. The processor can wait for the engine to complete processing of pipelined instructions of a first context before switching to another context, or the processor can halt the operation of the engine in the midst of one or more instructions to allow the engine to execute instructions corresponding to another context. The processor can affirmatively verify completion of tasks for a specific operation context.

    摘要翻译： 具有多个独立引擎的处理器可以同时支持多个独立的进程或操作上下文。 处理器可以独立地调度指令以供引擎执行。 处理器可以独立地切换引擎支持的操作上下文。 处理器可以通过控制引擎从一个操作上下文转换到下一个操作上下文的方式来保持在上下文切换期间由每个引擎执行的操作和数据处理的完整性。 处理器可以等待引擎在切换到另一个上下文之前完成对第一上下文的流水线指令的处理，或者处理器可以在一个或多个指令中停止发动机的操作，以允许引擎执行对应于 另一个上下文。 处理器可以肯定地验证特定操作上下文的任务完成。

    Shadow unit for shadowing circuit status
    5.
    发明授权
    Shadow unit for shadowing circuit status 有权
    阴影单元用于阴影电路状态

    公开(公告)号：US07937606B1

    公开(公告)日：2011-05-03

    申请号：US11437112

    申请日：2006-05-18

    申请人： Lincoln G. Garlick ,  Paolo E. Sabella ,  Samuel H. Duncan ,  Robert J. Hasslen

    发明人： Lincoln G. Garlick ,  Paolo E. Sabella ,  Samuel H. Duncan ,  Robert J. Hasslen

    IPC分类号： G06F1/04 ,  G06F15/177

    CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F11/3055 ,  G06F11/3089 ,  Y02D10/128 ,  Y02D10/171

    摘要： Generally, the present disclosure concerns systems and methods for shadowing status for a circuit with a shadow unit. In one aspect, a system comprises a first circuit in a first dynamic clock domain of a plurality of dynamic clock domains, a processor configured to execute software instructions to generate a request for a status of the first circuit, and a second circuit coupled to the first circuit and to the processor. The second circuit, outside the first dynamic clock domain, is configured to shadow a status of the first circuit and to respond to the request for the status of the first circuit with the shadowed status.

    摘要翻译： 通常，本公开涉及用于具有阴影单元的电路的阴影状态的系统和方法。 在一个方面，系统包括多个动态时钟域的第一动态时钟域中的第一电路，被配置为执行软件指令以产生对第一电路的状态的请求的处理器，以及耦合到 第一电路和处理器。 在第一动态时钟域之外的第二电路被配置为影响第一电路的状态并且响应于具有阴影状态的第一电路的状态的请求。

    Method, apparatus and article of manufacture for a transform module in a graphics processor
    7.
    发明授权
    Method, apparatus and article of manufacture for a transform module in a graphics processor 有权
    用于图形处理器中的变换模块的方法，装置和制品

    公开(公告)号：US07009607B2

    公开(公告)日：2006-03-07

    申请号：US09775086

    申请日：2001-01-31

    申请人： John Erik Lindholm ,  Simon Moy ,  David B. Kirk ,  Paolo E. Sabella

    发明人： John Erik Lindholm ,  Simon Moy ,  David B. Kirk ,  Paolo E. Sabella

    IPC分类号： G06T17/00

    CPC分类号： G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/50 ,  G06T15/503 ,  G06T15/506

    摘要： A method, apparatus and article of manufacture are provided for a transform system for graphics processing as a computer system or on a single integrated circuit. Included is an input buffer adapted for being coupled to a vertex attribute buffer for receiving vertex data therefrom. A multiplication logic unit has a first input coupled to an output of the input buffer. Also provided is an arithmetic logic unit having a first input coupled to an output of the multiplication logic unit. Coupled to an output of the arithmetic logic unit is an input of a register unit. An inverse logic unit is provided including an input coupled to the output of the arithmetic logic unit or the register unit for performing an inverse or an inverse square root operation. Further included is a conversion module coupled between an output of the inverse logic unit and a second input of the multiplication logic unit. In use, the conversion module serves to convert scalar vertex data to vector vertex data. Memory is coupled to the multiplication logic unit and the arithmetic logic unit. The memory has stored therein a plurality of constants and variables for being used in conjunction with the input buffer, the multiplication logic unit, the arithmetic logic unit, the register unit, the inverse logic unit, and the conversion module for processing the vertex data. Finally, an output converter is coupled to the output of the arithmetic logic unit for being coupled to a lighting module to output the processed vertex data thereto.

    摘要翻译： 提供了一种用于图形处理的变换系统作为计算机系统或单个集成电路的方法，装置和制品。 包括适于耦合到顶点属性缓冲器以从其接收顶点数据的输入缓冲器。 乘法逻辑单元具有耦合到输入缓冲器的输出的第一输入。 还提供了具有耦合到乘法逻辑单元的输出的第一输入的算术逻辑单元。 耦合到算术逻辑单元的输出是寄存器单元的输入。 提供了一个逆逻辑单元，其包括耦合到算术逻辑单元或寄存器单元的输出的输入，用于执行反或平方根操作。 还包括耦合在反逻辑单元的输出和乘法逻辑单元的第二输入之间的转换模块。 在使用中，转换模块用于将标量顶点数据转换为向量顶点数据。 存储器耦合到乘法逻辑单元和算术逻辑单元。 存储器中存储有多个常数和变量，用于与输入缓冲器，乘法逻辑单元，算术逻辑单元，寄存器单元，逆逻辑单元和用于处理顶点数据的转换模块结合使用。 最后，输出转换器耦合到算术逻辑单元的输出，用于耦合到照明模块，以将经处理的顶点数据输出到照明模块。

    Double-buffering of pixel data using copy-on-write semantics
    8.
    发明授权
    Double-buffering of pixel data using copy-on-write semantics 有权
    使用写时复制语义对像素数据进行双缓冲

    公开(公告)号：US06911983B2

    公开(公告)日：2005-06-28

    申请号：US10388112

    申请日：2003-03-12

    申请人： Paolo E. Sabella ,  Nicholas P. Witt

    发明人： Paolo E. Sabella ,  Nicholas P. Witt

    IPC分类号： G06F13/00 ,  G09G5/393 ,  G09G5/399

    CPC分类号： G09G5/393 ,  G06F3/1415 ,  G09G5/395 ,  G09G5/397 ,  G09G5/399 ,  G09G2310/04 ,  G09G2320/103 ,  G09G2350/00 ,  G09G2360/122 ,  G09G2360/127 ,  G09G2360/18

    摘要： Tile buffers in a graphics processing system are managed use “copy-on-write” semantics, in which tile data stored in a memory location is not transferred to another location until the tile data for one of the buffers is modified. Two memory spaces store tile data, and two logical buffers are used to access the memory spaces. For each tile, a tile association is maintained, indicating which of the two memory spaces is associated with each of the two logical buffers. To copy a tile of the first logical buffer to the second logical buffer, the tile association for the tile being copied is modified. Data for a tile is written to the memory space associated with a target logical buffer after ensuring that the tile association for the tile associates the target logical buffer with a different one of the two memory spaces from the other logical buffer.

    摘要翻译： 图形处理系统中的平铺缓冲器被管理使用“写时复制”语义，其中存储在存储器位置的瓦片数据不被传送到另一位置，直到修改了其中一个缓冲器的瓦片数据为止。 两个存储空间存储瓦片数据，并且使用两个逻辑缓冲器来访问存储器空间。 对于每个瓦片，保持瓦片关联，指示两个存储器空间中的哪一个与两个逻辑缓冲器中的每一个相关联。 要将第一个逻辑缓冲区的块复制到第二个逻辑缓冲区，将修改要复制的瓦片的瓦片关联。 在确保瓦片的瓦片关联将目标逻辑缓冲器与另一逻辑缓冲器中的两个存储器空间中的不同的一个相关联之后，瓦片的数据被写入与目标逻辑缓冲器相关联的存储器空间。