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    DIGITAL MEDIA PROCESSOR
    1.
    发明申请
    DIGITAL MEDIA PROCESSOR 审中-公开
    数字媒体处理器

    公开(公告)号：US20140055559A1

    公开(公告)日：2014-02-27

    申请号：US13568875

    申请日：2012-08-07

    申请人： Jen-Hsun Huang ,  Gerrit A. Slavenburg ,  Stephen D. Lew ,  John C. Schafer ,  Thomas F. Fox ,  Taner E. Ozcelik

    发明人： Jen-Hsun Huang ,  Gerrit A. Slavenburg ,  Stephen D. Lew ,  John C. Schafer ,  Thomas F. Fox ,  Taner E. Ozcelik

    IPC分类号： G06T15/00 ,  H04N13/00

    CPC分类号： G06T15/005 ,  G06F15/78 ,  G09G5/003 ,  G09G2360/02 ,  H04N13/161

    摘要： Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.

    摘要翻译： 为数字消费电子应用提供高度集成的数字媒体处理器的电路，方法和设备。 这些数字媒体处理器能够执行多格式音频，视频和图形信号的并行处理。 在一个实施例中，音频和视频信号可以从诸如天线，VCR，DVD以及诸如摄像机和调制解调器之类的网络设备的各种输入设备或设备接收，而输出音频和视频信号可以被提供给诸如 作为电视机，显示器和网络设备，如打印机和网络录像机。 本发明的另一实施例与诸如导航，娱乐，安全，存储器和网络设备的各种设备接口。 该实施例还可以被配置为用于数字电视，机顶盒或家庭服务器中。 在该配置中，可以从多个有线，卫星，因特网和消费者设备接收视频和音频流。

    METHODS FOR SCALABLY EXPLOITING PARALLELISM IN A PARALLEL PROCESSING SYSTEM
    3.
    发明申请
    METHODS FOR SCALABLY EXPLOITING PARALLELISM IN A PARALLEL PROCESSING SYSTEM 有权
    在平行处理系统中大量开发并行的方法

    公开(公告)号：US20110238955A1

    公开(公告)日：2011-09-29

    申请号：US13099035

    申请日：2011-05-02

    申请人： John R. Nickolls ,  Stephen D. Lew

    发明人： John R. Nickolls ,  Stephen D. Lew

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3851 ,  G06F9/30072 ,  G06F9/3012 ,  G06F9/3889 ,  G06F9/5066

    摘要： Parallelism in a parallel processing subsystem is exploited in a scalable manner. A problem to be solved can be hierarchically decomposed into at least two levels of sub-problems. Individual threads of program execution are defined to solve the lowest-level sub-problems. The threads are grouped into one or more thread arrays, each of which solves a higher-level sub-problem. The thread arrays are executable by processing cores, each of which can execute at least one thread array at a time. Thread arrays can be grouped into grids of independent thread arrays, which solve still higher-level sub-problems or an entire problem. Thread arrays within a grid, or entire grids, can be distributed across all of the available processing cores as available in a particular system implementation.

    摘要翻译： 并行处理子系统中的并行性以可扩展的方式被利用。 要解决的问题可以被分层分解成至少两个级别的子问题。 定义程序执行的各个线程来解决最低级别的问题。 线程被分组成一个或多个线程数组，每个线程数组都解决了较高级的子问题。 线程数组可以通过处理内核执行，每个核心可以一次执行至少一个线程数组。 线程数组可以分组成独立线程数组的网格，从而解决更高级的子问题或整个问题。 网格中的线程数组或整个网格可以分布在所有可用处理核心中，如特定系统实现中可用的。

    Method and apparatus for filtering video data using a programmable graphics processor
    4.
    发明授权
    Method and apparatus for filtering video data using a programmable graphics processor 有权
    使用可编程图形处理器对视频数据进行过滤的方法和装置

    公开(公告)号：US07876378B1

    公开(公告)日：2011-01-25

    申请号：US11957361

    申请日：2007-12-14

    申请人： Stephen D. Lew ,  Garry W. Amann ,  Hassane S. Azar

    发明人： Stephen D. Lew ,  Garry W. Amann ,  Hassane S. Azar

    IPC分类号： H04N5/917

    CPC分类号： H04N19/86 ,  H04N7/01 ,  H04N7/012

    摘要： Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.

    摘要翻译： 描述使用可编程图形处理器的视频滤波。 可编程图形处理器可以被编程为在可编程图形处理器内的片段处理流水线的单次传递中完成多个视频滤波操作。 诸如去隔行，色度上采样，缩放和去块之类的视频滤波功能可以由片段处理流水线执行。 片段处理流水线可以被编程为执行运动自适应去隔行，其中空间变异滤波器基于像素确定是否应当使用“bob”，“blend”或“weave”操作来处理隔行扫描 图片。

    Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior
    5.
    发明授权
    Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior 有权
    并行数据处理系统和方法使用协作线程数组和线程标识符值来确定处理行为

    公开(公告)号：US07861060B1

    公开(公告)日：2010-12-28

    申请号：US11305178

    申请日：2005-12-15

    申请人： John R. Nickolls ,  Stephen D. Lew

    发明人： John R. Nickolls ,  Stephen D. Lew

    IPC分类号： G06F15/16

    CPC分类号： G06F9/544 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/522

    摘要： Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an output data set. Each thread in a CTA has a unique identifier (thread ID) that can be assigned at thread launch time. The thread ID controls various aspects of the thread's processing behavior such as the portion of the input data set to be processed by each thread, the portion of an output data set to be produced by each thread, and/or sharing of intermediate results among threads. Mechanisms for loading and launching CTAs in a representative processing core and for synchronizing threads within a CTA are also described.

    摘要翻译： 并行数据处理系统和方法使用协同线程数组（CIA），即在输入数据集上同时执行相同程序的多线程组，以产生输出数据集。 CTA中的每个线程都有一个唯一的标识符（线程ID），可以在线程启动时分配。 线程ID控制线程的处理行为的各个方面，例如由每个线程处理的输入数据集的部分，由每个线程产生的输出数据集的部分和/或线程之间的中间结果的共享 。 还描述了在代表性处理核心中加载和启动CTA并在CTA内同步线程的机制。

    Platform-based idle-time processing
    6.
    发明授权
    Platform-based idle-time processing 有权
    基于平台的空闲时间处理

    公开(公告)号：US07779191B2

    公开(公告)日：2010-08-17

    申请号：US12182074

    申请日：2008-07-29

    申请人： Chien-Ping Lu ,  Stephen D. Lew ,  Robert William Chapman

    发明人： Chien-Ping Lu ,  Stephen D. Lew ,  Robert William Chapman

    IPC分类号： G06F9/48

    CPC分类号： G06F1/3203

    摘要： A system and method for transitions a computing system between operating modes that have different power consumption characteristics. When a system management unit (SMU) determines that the computing system is in a low activity state, the SMU transitions the central processing unit (CPU) into a low power operating mode after the CPU stores critical operating state of the CPU in a memory. The SMU then intercepts and processes interrupts intended for the CPU, modifying a copy of the critical operating state. This effectively extends the time during which the CPU stays in lower power mode. When the SMU determines that the computing system exits a low activity state, the copy of the critical operating state is stored in the memory and the SMU transitions the CPU into a high power operating mode using the modified critical operating state.

    摘要翻译： 一种用于在具有不同功耗特性的操作模式之间转换计算系统的系统和方法。 当系统管理单元（SMU）确定计算系统处于低活动状态时，在CPU将CPU的临界操作状态存储在存储器中之后，SMU将中央处理单元（CPU）转换为低功耗操作模式。 然后，SMU拦截并处理用于CPU的中断，修改关键操作状态的副本。 这有效地延长了CPU处于较低功耗模式的时间。 当SMU确定计算系统退出低活动状态时，关键操作状态的副本存储在存储器中，并且SMU使用修改的关键操作状态将CPU转换为高功率​​操作模式。

    Latency tolerant system for executing video processing operations
    8.
    发明授权
    Latency tolerant system for executing video processing operations 有权
    用于执行视频处理操作的延迟容忍系统

    公开(公告)号：US08687008B2

    公开(公告)日：2014-04-01

    申请号：US11267875

    申请日：2005-11-04

    申请人： Ashish Karandikar ,  Shirish Gadre ,  Stephen D. Lew

    发明人： Ashish Karandikar ,  Shirish Gadre ,  Stephen D. Lew

    IPC分类号： G06F15/16 ,  G06F15/80 ,  G06F13/14 ,  G09G5/39 ,  G09G5/36 ,  G06F7/32 ,  G06F13/00 ,  G06F15/00

    CPC分类号： G06T1/60 ,  G06F3/14 ,  G06F9/3851 ,  G06F9/3887 ,  G06F12/0877 ,  G06T1/20 ,  G09G5/37 ,  H04N19/42 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N19/82 ,  H04N19/85 ,  H04N19/86

    摘要： A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations, and a vector execution unit coupled to the host interface and configured to execute vector video processing operations. A command FIFO is included for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A DMA engine is built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading the command FIFO with data and instructions for the vector execution unit.

    摘要翻译： 用于执行视频处理操作的等待时间容限系统。 该系统包括用于实现视频处理器和主机CPU之间的通信的主机接口，耦合到主机接口并被配置为执行标量视频处理操作的标量执行单元，以及耦合到主机接口并被配置为执行 矢量视频处理操作。 包括指令FIFO，用于通过访问存储器命令FIFO使得矢量执行单元能够在需求驱动的基础上操作。 包括用于实现视频处理器和帧缓冲存储器之间的通信的存储器接口。 DMA引擎内置在存储器接口中，用于在多个不同存储器位置之间实现DMA传输，并且用于向命令FIFO加载用于向量执行单元的数据和指令。

    Stream processing in a video processor
    10.
    发明授权
    Stream processing in a video processor 有权
    视频处理器中的流处理

    公开(公告)号：US08416251B2

    公开(公告)日：2013-04-09

    申请号：US11267599

    申请日：2005-11-04

    申请人： Shirish Gadre ,  Ashish Karandikar ,  Stephen D. Lew

    发明人： Shirish Gadre ,  Ashish Karandikar ,  Stephen D. Lew

    IPC分类号： G09G5/39 ,  G09G5/36 ,  G06F15/167

    CPC分类号： G06T1/60 ,  G06F3/14 ,  G06F9/3851 ,  G06F9/3887 ,  G06F12/0877 ,  G06T1/20 ,  G09G5/37 ,  H04N19/42 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N19/82 ,  H04N19/85 ,  H04N19/86

    摘要： A stream based memory access system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A frame buffer memory is included for storing data for the scalar execution unit and the vector execution unit. A memory interface is included for establishing communication between the scalar execution unit and the vector execution unit and the frame buffer memory. The frame buffer memory comprises a plurality of tiles. The memory interface implements a first sequential access of tiles and implements a second stream comprising a second sequential access of tiles for the vector execution unit or the scalar execution unit.

    摘要翻译： 一种用于视频处理器的基于流的存储器访问系统，用于执行视频处理操作。 视频处理器包括被配置为执行标量视频处理操作的标量执行单元和被配置为执行向量视频处理操作的向量执行单元。 包括用于存储用于标量执行单元和向量执行单元的数据的帧缓冲存储器。 包括存储器接口，用于建立标量执行单元与向量执行单元与帧缓冲存储器之间的通信。 帧缓冲存储器包括多个瓦片。 存储器接口实现瓦片的第一顺序访问，并且实现包括用于向量执行单元或标量执行单元的瓦片的第二顺序访问的第二流。