Data integrity and cross-check code with logical block address
    1.
    发明授权
    Data integrity and cross-check code with logical block address 失效
    具有逻辑块地址的数据完整性和交叉校验码

    公开(公告)号:US5805799A

    公开(公告)日:1998-09-08

    申请号:US566361

    申请日:1995-12-01

    摘要: According to the invention, a data integrity code including logical block address ("LBA") and circuit implementation are provided. The code and implementing circuitry are utilized to enable data block LBA verification during a block transfer and retrieval process. The preferred data integrity code has embedded LBA information and also serves as a crosscheck code used to detect miscorrection by an error correction code ("ECC"). In a preferred disk drive embodiment, data integrity block ("DIB") is provided to verify that the LBA value associated with a given data block in a host interface matches the value associated with that same data block in a buffer memory and in a data sequencer. In a preferred method of use, data integrity/cross-check redundancy with LBA is appended to data blocks transmitted to a buffer memory and verified after the data block has been transferred from the buffer. After verification, the LBA is preferably written to the storage medium together with its associated data block to enable later LBA verification for blocks recovered from the storage medium. The LBA may also be verified when the data block is transferred back to a host from the buffer memory.

    摘要翻译: 根据本发明,提供了包括逻辑块地址(“LBA”)和电路实现的数据完整性代码。 代码和实现电路用于在块传输和检索过程期间启用数据块LBA验证。 优选的数据完整性代码具有嵌入的LBA信息,并且还用作用于通过纠错码(“ECC”)检测错误纠错的交叉检查代码。 在优选的磁盘驱动器实施例中,提供数据完整性块(“DIB”)以验证与主机接口中的给定数据块相关联的LBA值是否与缓冲存储器中的相同数据块相关联的值和数据 音序器 在优选的使用方法中,利用LBA的数据完整性/交叉校验冗余被附加到发送到缓冲存储器的数据块,并且在从缓冲器传送数据块之后验证。 在验证之后,优选地将LBA与其相关联的数据块一起写入存储介质,以便对从存储介质恢复的块进行后续的LBA验证。 当数据块从缓冲存储器传回主机时,也可以验证LBA。

    Amplifier gain control method using conditional updating
    2.
    发明授权
    Amplifier gain control method using conditional updating 失效
    使用条件更新的放大器增益控制方法

    公开(公告)号:US06195028B1

    公开(公告)日:2001-02-27

    申请号:US09281606

    申请日:1999-03-30

    IPC分类号: H03M100

    摘要: In a peak detection system having a variable gain amplifier (VGA), a counter is initialized and a countdown is triggered. Each time a qualified peak is detected, the counter is re-initialized. If the countdown is completed, the VGA gain is updated. This method can be used to boost amplifier gain that is too low to generate a qualifying threshold, even while overlooking short periods of very low output.

    摘要翻译: 在具有可变增益放大器(VGA)的峰值检测系统中,计数器被初始化并且触发倒计数。 每次检测到合格的峰值时,重新初始化计数器。 如果倒计时完成,则VGA增益更新。 该方法可以用于升高放大器增益,太低以至于无法产生限定门槛,即使在忽视短时间内输出非常低的情况下也是如此。

    Rate 4/5 trellis code for PR4 channels with improved error propagation
    3.
    发明授权
    Rate 4/5 trellis code for PR4 channels with improved error propagation 失效
    为PR4通道提供4/5格码,改进了错误传播

    公开(公告)号:US5691993A

    公开(公告)日:1997-11-25

    申请号:US483117

    申请日:1995-06-07

    申请人: Lisa Fredrickson

    发明人: Lisa Fredrickson

    摘要: A digital communication apparatus transmits sectors of digital values that include error correction values used to detect and correct errors within the sector. Each sector consists of a number of blocks and the error correction values of each block are useful in correcting up to a maximum number of erroneous digital units in that block. The digital communication apparatus encodes the blocks of digital units to transmit them through a channel and then decodes the channel's representation of those encoded blocks, where the channel's representation occasionally contains burst errors. The encoding and decoding is performed in a manner that reduces the number of consecutive erroneous digital units caused by any one burst error to a number less than the number of blocks in a sector, ensuring that the error burst corrupts at most one digital unit in each block.

    摘要翻译: 数字通信装置发送包括用于检测和校正扇区内的错误的纠错值的数字值的扇区。 每个扇区由多个块组成,并且每个块的纠错值可用于校正该块中最多数量的错误数字单元。 数字通信装置对数字单元的块进行编码,以通过信道发送它们,然后解码通道的那些编码块的表示,其中信道的表示偶尔包含突发错误。 执行编码和解码的方法是将由任何一个突发错误引起的连续的错误数字单元的数量减少到小于扇区中的块的数量的数量,确保错误突发在每个数据单元中最多破坏一个数字单元 块。

    Trellis codes with algebraic constraints for input restricted partial
response channels
    4.
    发明授权
    Trellis codes with algebraic constraints for input restricted partial response channels 失效
    用于输入限制部分响应信道的代数约束的网格码

    公开(公告)号:US5485472A

    公开(公告)日:1996-01-16

    申请号:US242942

    申请日:1994-05-16

    申请人: Lisa Fredrickson

    发明人: Lisa Fredrickson

    CPC分类号: H03M13/25 H03M13/31

    摘要: A method for constructing trellis codes and an apparatus for providing trellis codes with increased minimum distance between output sequences of partial response channels with constrained inputs. A Viterbi detector expands a conventional trellis structure for the channel incorporating additional states interconnected such that a preselected function associates each state in the trellis with an algebraic evaluation of a polynomial at a particular element of a finite field. The detector trellis is time-varying such that only certain values of the preselected function are allowed every m bits. The time-variation assures that there are no minimum distance extensions of erroneous sequences beyond a predetermined length in the trellis. Reliability of storage channels is desirably increased, because more noise is required to overcome the additional distance and cause an error in distinguishing the correct encoded sequence.

    摘要翻译: 一种用于构建网格码的方法,以及用于提供具有约束输入的部分响应信道的输出序列之间具有增加的最小距离的网格码的装置。 维特比检测器扩展用于通道的常规网格结构,该通道包含互连的附加状态,使得预选功能将网格中的每个状态与有限域的特定元素处的多项式的代数估计相关联。 检测器网格是时变的,使得每m位只允许预选功能的某些值。 时间变化确保了网格中没有超出预定长度的错误序列的最小距离延伸。 期望增加存储通道的可靠性,因为需要更多的噪声来克服附加距离并导致区分正确编码序列的错误。

    Construction Methods for Finite Fields with Split-optimal Multipliers
    5.
    发明申请
    Construction Methods for Finite Fields with Split-optimal Multipliers 审中-公开
    具有分裂最优乘数的有限域的构造方法

    公开(公告)号:US20140012889A1

    公开(公告)日:2014-01-09

    申请号:US13541739

    申请日:2012-07-04

    申请人: Lisa Fredrickson

    发明人: Lisa Fredrickson

    IPC分类号: G06F7/44

    CPC分类号: G06F7/724

    摘要: Improved multiplier construction methods facilitate efficient multiplication in finite fields. Implementations include digital logic circuits and user scaleable software. Lower logical circuit complexity is achieved by improved resource sharing with subfield multipliers. Split-optimal multipliers meet a lower bound measuring complexity. Multiplier construction methods are applied repeatedly to build efficient multipliers for large finite fields from small subfield components.An improved finite field construction method constructs arbitrarily large finite fields using search results from a small starting field, building successively larger fields from the bottom up, without the need for successively larger searches. The improved method constructs arbitrarily large finite fields with limited construction effort using a polynomial constant equal to the product of a deterministic product term and a selectable small field scalar. The polynomials used in the improved method feature sparse constants facilitating low complexity multiplication.

    摘要翻译: 改进的乘法器构造方法有助于有限域中的有效乘法。 实现包括数字逻辑电路和用户可缩放软件。 通过改进与子域乘法器的资源共享来实现较低的逻辑电路复杂度。 分裂最优乘法器满足下限测量复杂度。 乘法构造方法反复应用,为小型子场分量的大有限域建立有效乘数。 改进的有限域构造方法使用来自小起始场的搜索结果构建任意大的有限域,从下而上构建连续较大的场,而不需要连续更大的搜索。 改进的方法使用等于确定性乘积项和可选择的小场标量的乘积的多项式常数来构造具有有限构造力的任意大的有限域。 在改进的方法中使用的多项式特征稀疏常数,促进低复杂度乘法。

    High throughput Reed-Solomon encoder
    7.
    发明授权
    High throughput Reed-Solomon encoder 有权
    高通量Reed-Solomon编码器

    公开(公告)号:US07082564B2

    公开(公告)日:2006-07-25

    申请号:US10251774

    申请日:2002-09-23

    IPC分类号: H03M13/00

    CPC分类号: H03M13/158

    摘要: Reed-Solomon encoders providing support for multiple codes in a simple architecture having a reduced number of Galois field multipliers. Rather than implementing n subfilters each representing an individual degree polynomial filter as in conventional Reed-Solomon encoder, multiple degree polynomials are factored in a way which is convenient to a desired plurality of Reed-Solomon codes. Thus, not only are the number of required Galois field multipliers reduced, but support for different Reed-Solomon codes is provided with a minimized number of Galois field multipliers. Preferred embodiments in compliance with the proposed 802.16.1 wireless standard support up to sixteen Reed-Solomon codes all within a single architecture, including sixteen subfilters, either cascaded or in parallel. Each of the individual filters balances and reduces critical path lengths in the Reed-Solomon encoder, and reduces the loading of critical nets, resulting in a Reed-Solomon encoder with a greater throughput for a given technology.

    摘要翻译: Reed-Solomon编码器在具有减少数量的伽罗瓦域乘法器的简单架构中提供对多个代码的支持。 与传统的里德 - 所罗门编码器一样,不是实现每个表示个体度多项式滤波器的n个子滤波器,而是以对所期望的多个Reed-Solomon码的方便的方式对多度多项式进行因子分解。 因此,不仅所需的伽罗瓦域乘法器的数量减少,而且对不同里德 - 所罗门码的支持被提供有最小数目的伽罗瓦域乘法器。 符合所提出的802.16.1无线标准的优选实施例在单个架构内支持多达16个Reed-Solomon码,包括级联或并行的16个子滤波器。 每个单独的滤波器平衡并减少Reed-Solomon编码器中的关键路径长度,并减少关键网络的负载,从而为给定技术带来更高吞吐量的Reed-Solomon编码器。

    Matched spectral null encoder/decoder
    8.
    发明授权
    Matched spectral null encoder/decoder 失效
    匹配频谱零编码器/解码器

    公开(公告)号:US5801649A

    公开(公告)日:1998-09-01

    申请号:US817865

    申请日:1997-04-21

    申请人: Lisa Fredrickson

    发明人: Lisa Fredrickson

    摘要: An encoder for matched spectral null binary codes is described, particularly for 12B/15B codes. The codeword trellis is partitioned into two or more subtrellises, and each subtrellis is encoded separately. The codeword is the concatenation of the codewords produced by the subtrellises. Some valid sequences have to be excluded, in order to ensure that all concatenations are valid, but the storage requirements, are greatly reduced.

    摘要翻译: PCT No.PCT / US96 / 12680 Sec。 371日期1997年04月21日 102(e)日期1997年4月21日PCT 1996年8月2日PCT公布。 出版物WO97 / 06624 日期1997年2月20日描述了用于匹配频谱零二进制码的编码器,特别是对于12B / 15B码。 码字网格划分成两个或多个子树,每个子树被分开编码。 码字是由子突击产生的码字的级联。 必须排除一些有效的序列,以确保所有连接都有效,但存储要求大大降低。

    Permuted trellis codes for input restricted partial response channels
    10.
    发明授权
    Permuted trellis codes for input restricted partial response channels 失效
    输入限制部分响应通道的格子码

    公开(公告)号:US5497384A

    公开(公告)日:1996-03-05

    申请号:US174904

    申请日:1993-12-29

    摘要: Maximum likelihood detection of a trellis code using a Viterbi detector constructed from a time-varying trellis structure that is associated with a partial response channel and consists of connected trellises with periodically repeated patterns of nodes and subtrellises of said trellises. Each subtrellis has nodes representing a current state of the channel and value of a predetermined tracked attribute. A survivor metric and a survivor sequence from a node at the end of one subtrellis are reassigned to a node at the beginning of an adjacent subtrellis having a different value of the tracked attribute for increasing minimum distance properties, reducing error event length and improving code constraints for timing and gain control. The one subtrellis and adjacent subtrellis may be within a single trellis or in adjacent trellises.

    摘要翻译: 使用由与部分响应信道相关联的时变网格结构构成的维特比检测器的网格码的最大似然检测,并且由具有所述网格的节点和子树的周期性重复模式的连接网格组成。 每个子伞具有表示通道的当前状态和预定跟踪属性的值的节点。 来自一个子结尾处的节点的幸存者度量和幸存者序列被重新分配给具有跟踪属性的不同值的相邻子树的开始处的节点,用于增加最小距离属性,减少错误事件长度和改进代码约束 用于定时和增益控制。 一个子伞和相邻的子伞可以在单个网格内或相邻的网格中。