Amplifier gain control method using conditional updating
    1.
    发明授权
    Amplifier gain control method using conditional updating 失效
    使用条件更新的放大器增益控制方法

    公开(公告)号:US06195028B1

    公开(公告)日:2001-02-27

    申请号:US09281606

    申请日:1999-03-30

    IPC分类号: H03M100

    摘要: In a peak detection system having a variable gain amplifier (VGA), a counter is initialized and a countdown is triggered. Each time a qualified peak is detected, the counter is re-initialized. If the countdown is completed, the VGA gain is updated. This method can be used to boost amplifier gain that is too low to generate a qualifying threshold, even while overlooking short periods of very low output.

    摘要翻译: 在具有可变增益放大器(VGA)的峰值检测系统中,计数器被初始化并且触发倒计数。 每次检测到合格的峰值时,重新初始化计数器。 如果倒计时完成,则VGA增益更新。 该方法可以用于升高放大器增益,太低以至于无法产生限定门槛,即使在忽视短时间内输出非常低的情况下也是如此。

    Adaptive magnetic recording and readback system
    2.
    发明授权
    Adaptive magnetic recording and readback system 失效
    自适应磁记录和回读系统

    公开(公告)号:US5107378A

    公开(公告)日:1992-04-21

    申请号:US607646

    申请日:1990-10-29

    IPC分类号: G11B5/012 G11B5/09 G11B20/10

    摘要: A method and related system for use with a disk drive are disclosed for adjusting the current level emanating from a read/write head during recording of data onto a disk to compensate for differences in read/write head and disk relationships. Also, a method and related system are disclosed for determining the optimum slimming constant to be utilized to minimize data pulse peak shifts to compensate for differences in read/write head and disk relationships.

    摘要翻译: 公开了一种用于磁盘驱动器的方法和相关系统,用于在将数据记录到磁盘上时调整从读/写头发出的当前电平,以补偿读/写磁头和磁盘关系的差异。 此外,公开了一种用于确定要用于最小化数据脉冲峰值偏移以补偿读/写磁头和磁盘关系中的差异的最佳减肥常数的方法和相关系统。

    Meter control circuit
    4.
    发明授权
    Meter control circuit 失效
    仪表控制电路

    公开(公告)号:US4131846A

    公开(公告)日:1978-12-26

    申请号:US805722

    申请日:1977-06-13

    申请人: Dennis C. Stone

    发明人: Dennis C. Stone

    CPC分类号: G01R1/30 G01R15/005

    摘要: In combination with a meter movement having a pointer movable over a variable value indicating scale having numbered variable value indicating marks forming respective scale segments having substantially different compression or expansion ratios and representing progressively increasing variable values over the entire extent of said segments, a meter control circuit comprising respective amplifiers for controlling the variation of pointer movement over said respective segments of said scale, each of the amplifiers being capable of producing an output which reaches a maximum possible output level when the signal fed to the input thereof is of a value which is to move the pointer of said meter movement to the uppermost point of the associated segment of the scale, means for summing the outputs of said respective amplifiers and feeding the same to said meter movement. Signal directing means are provided for respectively directing to said amplifiers signals resulting from the flow of respective incremental ranges of current values in said input circuits to the amplifiers to cause the meter movement pointer to traverse said respective segments of said scale. The signal directing means directs said signals to the amplifier associated with the next highest scale segment of said meter movement scale only after the output of the amplifier associated with the next lowest segment of the scale has reached its maximum output value.

    摘要翻译: 结合具有可移动在可变值上的指示器的指示器,该指示器具有编号的变量值,该标度具有指示形成具有基本上不同的压缩或膨胀比的相应缩放部分的标记,并且表示在所述段的整个范围上逐渐增加的可变值, 电路包括用于控制所述刻度的所述各个段上的指针移动的变化的各个放大器,每个放大器能够产生一个输出,当输入到其输入端的信号为一个值时,该输出达到最大可能的输出电平 将所述仪表移动的指针移动到标尺的相关联的段的最高点,用于将所述各个放大器的输出相加并将其馈送到所述仪表运动的装置。 信号引导装置被提供用于分别引导到所述放大器的信号,所述信号是由所述输入电路中的各个当前值的增加范围流向放大器而产生的,以使得仪表移动指针穿过所述标尺的所述各个段。 信号指示装置仅在与标尺的下一个最低段相关联的放大器的输出已经达到其最大输出值之后,将所述信号引导到与所述仪表运动刻度的下一个最高刻度段相关联的放大器。

    Method and apparatus for a digital peak detection system including a
countdown timer
    5.
    发明授权
    Method and apparatus for a digital peak detection system including a countdown timer 失效
    一种包括倒数计时器的数字峰值检测系统的方法和装置

    公开(公告)号:US06100829A

    公开(公告)日:2000-08-08

    申请号:US954167

    申请日:1997-10-20

    摘要: A digital peak detection system digitizes analog signals and provides absolute values to a series of one cycle delays, and to a sequence of comparator stages. Each digital sample is parallel compared to a number of preceding samples equal to the number of active comparator stages. Control signals activate comparator stages to determine sample comparison window length, including lengths exceeding the number of samples between recorded peaks. Peak detection is optimized using a variable gain amplifier whose gain is updated based upon amplitude difference between actual and desired peak samples. When sample amplitudes are smaller than a qualifier threshold, a countdown timer increases amplifier gain after lapse of a programmed time without detecting a qualified pulse. Gain is also updated when the analog to digital converter saturates. Initial gain values can be programmed, and gain stored at the end of a servo mode for future use in reducing gain control loop convergence time.

    摘要翻译: 数字峰值检测系统对模拟信号进行数字化,并提供一系列一个周期延迟的绝对值,以及一系列比较器级。 每个数字样本与先前的多个样本相比较,与等效于有效比较器级的数量相比较。 控制信号激活比较器级,以确定采样比较窗口长度,包括长度超过记录峰值之间的采样数。 使用可变增益放大器优化峰值检测,该增益放大器基于实际峰值和期望峰值样本之间的幅度差值来更新增益。 当采样幅度小于限定阈值时,倒计时定时器在经过编程时间之后增加放大器增益,而不检测合格脉冲。 当模数转换器饱和时,增益也会更新。 可以对初始增益值进行编程,并在伺服模式结束时存储增益,以备将来用于降低增益控制回路收敛时间。

    Circuit for testing high frequency current amplifying capability of
bipolar transistors
    6.
    发明授权
    Circuit for testing high frequency current amplifying capability of bipolar transistors 失效
    用于测试双极晶体管的高频电流放大能力的电路

    公开(公告)号:US4135153A

    公开(公告)日:1979-01-16

    申请号:US792134

    申请日:1977-04-29

    申请人: Dennis C. Stone

    发明人: Dennis C. Stone

    IPC分类号: G01R31/26 G01R31/22

    CPC分类号: G01R31/2608

    摘要: A transistor test circuit provides for the selection of preferably three widely differing test frequencies for testing transistors normally having respectively relatively small, intermediate and large frequency gain-bandwidth product characteristics. These test frequencies are each much greater than the assumed normal cut-off frequency of the transistors to be tested thereby, and preferably only a fraction of the frequency at which the current gain of normal transistors would decrease to one. The test circuit is designed to form a linear amplifier circuit with the transistor under test and is provided with an automatic base drive control circuit which provides a substantially fixed predetermined DC collector current, despite wide variations in the current gain between different transistors being tested. The circuit further includes an indicating means for displaying the product of the selected test frequency and the current gain of the transistor under test, as indicated by the amplitude of the amplified test frequency signal in the collector circuit of the transistor under test.

    摘要翻译: 晶体管测试电路提供优选地选择三个广泛不同的测试频率,用于测试通常具有分别相对较小,中等和大频率增益带宽乘积特性的晶体管。 这些测试频率都远大于要测试的晶体管的假定正常截止频率,并且优选地,只有正常晶体管的电流增益将减小到1的频率的一部分。 测试电路被设计成与被测晶体管形成线性放大器电路,并且设置有自动基极驱动控制电路,其提供基本上固定的预定直流集电极电流,尽管在被测试的不同晶体管之间的电流增益的变化很大。 该电路还包括用于显示被测试晶体管的所选测试频率和当前增益的乘积的指示装置,如被测晶体管的集电极电路中放大的测试频率信号的幅度所示。