公开(公告)号：US11871572B2

公开(公告)日：2024-01-09

申请号：US17561564

申请日：2021-12-23

Applicant: Lodestar Licensing Group LLC

Inventor： Shyam Surthi ,  Davide Resnati ,  Paolo Tessariol ,  Richard J. Hill ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L29/788 ,  H01L29/792 ,  H10B43/27 ,  H01L29/49 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02236 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4991 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7883 ,  H01L29/792 ,  H10B41/27

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions. High-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically-extending linear segments which are vertically spaced from one another. Charge-blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically-extending linear segments which are vertically spaced from one another. Charge-storage material is adjacent to the charge-blocking material and is configured as an arrangement of third vertically-extending linear segments which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies and methods of forming integrated assemblies.