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    IMAGE PROCESSOR FORMED IN AN ARRAY OF MEMORY CELLS
    2.
    发明公开
    IMAGE PROCESSOR FORMED IN AN ARRAY OF MEMORY CELLS 审中-公开

    公开(公告)号：US20240305759A1

    公开(公告)日：2024-09-12

    申请号：US18667592

    申请日：2024-05-17

    申请人： Lodestar Licensing Group LLC

    发明人： Fa-Long Luo ,  Jaime C. Cummins ,  Tamara Schmitz

    IPC分类号： H04N9/67 ,  G06F17/16 ,  H04N1/60 ,  H04N23/88

    CPC分类号： H04N9/67 ,  G06F17/16 ,  H04N1/6027 ,  H04N1/6077 ,  H04N23/88

    摘要： Apparatuses, systems, and methods related to an image processor formed in an array of memory cells are described. An image processor as described herein is configured to reduce complexity and power consumption and/or increase data access bandwidth by performing image processing in the array of memory cells relative to image processing by a host processor external to the memory array. For instance, one apparatus described herein includes sensor circuitry configured to provide an input vector, as a plurality of bits that corresponds to a plurality of color components for an image pixel, and an image processor formed in an array of memory cells. The image processor is coupled to the sensor circuitry to receive the plurality of bits of the input vector. The image processor is configured to perform a color correction operation in the array by performing matrix multiplication on the input vector and a parameter matrix to determine an output vector that is color corrected.

    Wireless devices and systems including examples of compensating I/Q imbalance with neural networks or recurrent neural networks
    3.
    发明授权
    Wireless devices and systems including examples of compensating I/Q imbalance with neural networks or recurrent neural networks 有权

    公开(公告)号：US12040920B2

    公开(公告)日：2024-07-16

    申请号：US18052797

    申请日：2022-11-04

    申请人： Lodestar Licensing Group LLC

    发明人： Fa-Long Luo

    IPC分类号： H04L25/03 ,  G06N3/045 ,  G06N3/084 ,  H04L25/02

    CPC分类号： H04L25/03165 ,  G06N3/045 ,  G06N3/084 ,  H04L25/0254 ,  H04L2025/03464

    摘要： Examples described herein include methods, devices, and systems which compensates input data for I/Q imbalance or noise related thereto to generate compensated input data. In doing such the above compensation, during an uplink transmission time interval (TTI), a switch path is activated to provide converted input data to a receiver stage including a recurrent neural network (RNN). The RNN calculates an error representative of the noise based partly on the input signal to be transmitted and a feedback signal to generate filter coefficient data associated with the I/Q imbalance. The feedback signal is provided, after processing through the receiver, to the RNN. During an uplink TTI, the converted input data is transmitted as the RF wireless transmission via an RF antenna. During a downlink TTI, the switch path is deactivated and the receiver stage receives an additional RF wireless transmission to be processed in the receiver stage.

    Apparatus and method for image signal processing
    4.
    发明授权
    Apparatus and method for image signal processing 有权

    公开(公告)号：US11991488B2

    公开(公告)日：2024-05-21

    申请号：US17941181

    申请日：2022-09-09

    申请人： Lodestar Licensing Group LLC

    发明人： Fa-Long Luo ,  Jaime C. Cummins ,  Tamara Schmitz

    IPC分类号： H04N9/67 ,  G06F17/16 ,  H04N1/60 ,  H04N23/88

    CPC分类号： H04N9/67 ,  G06F17/16 ,  H04N1/6027 ,  H04N1/6077 ,  H04N23/88

    摘要： Apparatuses, systems, and methods related to an image processor formed in an array of memory cells are described. An image processor as described herein is configured to reduce complexity and power consumption and/or increase data access bandwidth by performing image processing in the array of memory cells relative to image processing by a host processor external to the memory array. For instance, one apparatus described herein includes sensor circuitry configured to provide an input vector, as a plurality of bits that corresponds to a plurality of color components for an image pixel, and an image processor formed in an array of memory cells. The image processor is coupled to the sensor circuitry to receive the plurality of bits of the input vector. The image processor is configured to perform a color correction operation in the array by performing matrix multiplication on the input vector and a parameter matrix to determine an output vector that is color corrected.

    MEMORY POOLING BETWEEN SELECTED MEMORY RESOURCES
    6.
    发明公开
    MEMORY POOLING BETWEEN SELECTED MEMORY RESOURCES 审中-公开

    公开(公告)号：US20240103929A1

    公开(公告)日：2024-03-28

    申请号：US18225548

    申请日：2023-07-24

    申请人： Lodestar Licensing Group, LLC

    发明人： Aaron P. Boehm ,  Glen E. Hush ,  Fa-Long Luo

    IPC分类号： G06F9/50 ,  G06F12/02 ,  G06F12/14

    CPC分类号： G06F9/5061 ,  G06F12/023 ,  G06F12/1425 ,  G06F2212/1016 ,  G06F2212/1052

    摘要： Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

    APPARATUSES AND METHODS FOR ORDERING BITS IN A MEMORY DEVICE
    7.
    发明公开
    APPARATUSES AND METHODS FOR ORDERING BITS IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240036875A1

    公开(公告)日：2024-02-01

    申请号：US18378044

    申请日：2023-10-09

    申请人： Lodestar Licensing Group LLC

    发明人： Glen E. Hush ,  Aaron P. Boehm ,  Fa-Long Luo

    IPC分类号： G06F9/38 ,  G06F9/30 ,  G11C7/10 ,  G11C7/08

    CPC分类号： G06F9/3856 ,  G06F9/30018 ,  G11C7/1006 ,  G06F9/3001 ,  G11C7/08 ,  G06F9/30032

    摘要： Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.

    Wireless devices and systems including examples of configuration modes for baseband units and remote radio heads
    8.
    发明授权
    Wireless devices and systems including examples of configuration modes for baseband units and remote radio heads 有权

    公开(公告)号：US12089232B2

    公开(公告)日：2024-09-10

    申请号：US18306694

    申请日：2023-04-25

    申请人： Lodestar Licensing Group LLC

    发明人： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

    IPC分类号： H04W72/29 ,  H04W88/08

    CPC分类号： H04W72/29 ,  H04W88/085 ,  Y02D30/70

    摘要： Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system allocates the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.