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    Reduced complexity maximum likelihood decoder for MIMO communications
    4.
    发明授权
    Reduced complexity maximum likelihood decoder for MIMO communications 有权
    用于MIMO通信的复杂度最小似然解码器

    公开(公告)号：US07965782B1

    公开(公告)日：2011-06-21

    申请号：US11801786

    申请日：2007-05-11

    申请人： Logeshwaran Vijayan ,  Partha Sarathy Murali ,  Sundaram Vanka

    发明人： Logeshwaran Vijayan ,  Partha Sarathy Murali ,  Sundaram Vanka

    IPC分类号： H04L5/12

    CPC分类号： H04L25/0204 ,  H04L25/0246 ,  H04L25/03006 ,  H04L25/067 ,  H04L2025/03426

    摘要： A reduced complexity maximum likelihood decoder receives a stream of symbols Y and channel estimate H. A transformation converts Y and H into Z and R by computing matrix R, such that the product of R and Q produces matrix H. A second transformation column-swaps matrix H to form H′, thereafter generating Q′ and R′ subject to the same constraints as was described for Q and R. Transformed variables Z and Z′ are formed by multiplying Y by QH and Q′H, respectively. Table entries with Z and R and Z′ and R′ have entries of all possible x2 accompanied by estimates of x1 derived from x2 and Z, and similar entries of all possible x1 accompanied by estimates of x2 derived from x1 and Z′. Hard and soft decisions are made by finding the minimum distance metric of the combined entries of the first and second table.

    摘要翻译： 降低的复杂度最大似然解码器接收码流Y和信道估计H.变换通过计算矩阵R将Y和H转换成Z和R，使得R和Q的乘积产生矩阵H.第二变换列交换 矩阵H形成H'，之后产生与对Q和R所述相同约束的Q'和R'。变换的变量Z和Z'分别通过将Y乘以QH和Q'H来形成。 具有Z和R以及Z'和R'的表条目具有所有可能的x2的条目，伴随着从x2和Z导出的x1的估计，以及所有可能的x1的类似条目，伴随着从x1和Z'得到的x2的估计。 通过找到第一和第二表的组合条目的最小距离度量来进行硬和软判决。

    Noise estimator for a communications system
    5.
    发明授权
    Noise estimator for a communications system 有权
    通信系统的噪声估计器

    公开(公告)号：US07634000B1

    公开(公告)日：2009-12-15

    申请号：US11439000

    申请日：2006-05-22

    申请人： Vaidyanathan Karthik ,  Partha Sarathy Murali ,  Sundaram Vanka

    发明人： Vaidyanathan Karthik ,  Partha Sarathy Murali ,  Sundaram Vanka

    IPC分类号： H04B3/46

    CPC分类号： H04L27/2647 ,  H04B17/336

    摘要： A SINR estimator receiving a symbol stream has a delay element coupled to the symbol stream to produce a delayed symbol stream, which is also coupled to a conjugator. A first multiplier forms a product from the symbol stream and the output of the conjugator, thereafter summing these values over an interval L and scaling by L to form a correlated power estimate Cn. A second multiplier forms a product from the symbol stream which is multiplied by the conjugate of the input, thereafter summing these values over the preamble interval 2L and scaling by 2L to form a non-correlated power estimate Pn. Cn and Pn are compared to generate an SINR estimate.

    摘要翻译： 接收符号流的SINR估计器具有耦合到符号流的延迟元件以产生延迟的符号流，其也耦合到共轭器。 第一乘法器从符号流和共轭器的输出形成乘积，然后在一个间隔L上对这些值进行求和，并用L缩放以形成相关的功率估计Cn。 第二乘法器从符号流中乘以乘以输入的共轭，然后在前导码间隔2L上对这些值进行求和，并缩放2L以形成非相关功率估计Pn。 将Cn和Pn进行比较以产生SINR估计。

    Quantizer responsive to noise level for a wireless communications system
    6.
    发明授权
    Quantizer responsive to noise level for a wireless communications system 有权
    量化器响应于无线通信系统的噪声电平

    公开(公告)号：US07295144B1

    公开(公告)日：2007-11-13

    申请号：US11438999

    申请日：2006-05-22

    申请人： Vaidyanathan Karthik ,  Partha Sarathy Murali ,  Sundaram Vanka

    发明人： Vaidyanathan Karthik ,  Partha Sarathy Murali ,  Sundaram Vanka

    IPC分类号： H04N7/26

    CPC分类号： H04L25/067 ,  H04B17/336 ,  H04L1/0054 ,  H04L27/261 ,  H04L27/2647

    摘要： A quantizer has a plurality of decision blocks, each coupled from input to output, where each decision blocks output generates a binary value that is an unchanged decision block input if the decision block input is below the threshold input level divided by a power of 2, or the decision block subtracts a threshold divided by the power of 2 and passes this result as the decision block output. The quantizer output is formed from the bits of each comparison from each decision block. The threshold is developed from a channel noise variance which may be multiplied by a scale factor related to coding type and rate. In this manner, a large number of input bits to be quantized may be converted to a smaller number of quantizer output bits, while preserving the dynamic range information required to correctly decode signals passed through a communications channel having multi-path frequency selective fading.

    摘要翻译： 量化器具有多个决定块，每个决定块从输入到输出耦合，其中如果判定块输入低于门限输入电平除以2的幂，则每个判定块输出产生二进制值，该二进制值是不变的判定块输入， 或决策块减去除以2的幂的阈值，并将该结果作为判定块输出。 量化器输出由每个判定块的每个比较的比特形成。 阈值是从可能与编码类型和速率相关的比例因子乘以的信道噪声方差产生的。 以这种方式，可以将要量化的大量输入比特转换为较少数量的量化器输出比特，同时保留正确解码通过具有多径频率选择性衰落的通信信道的信号所需的动态范围信息。

    Channel estimation filter for OFDM receiver
    7.
    发明授权
    Channel estimation filter for OFDM receiver 有权
    OFDM接收机的信道估计滤波器

    公开(公告)号：US08259786B2

    公开(公告)日：2012-09-04

    申请号：US12368431

    申请日：2009-02-10

    申请人： Partha Sarathy Murali ,  Kashiviswanath Nethi ,  Karthik Vaidyanathan ,  Sundaram Vanka

    发明人： Partha Sarathy Murali ,  Kashiviswanath Nethi ,  Karthik Vaidyanathan ,  Sundaram Vanka

    IPC分类号： H03H7/30

    CPC分类号： H04L27/2647 ,  H04L25/022 ,  H04L25/03159

    摘要： A channel smoothing filter with a finite impulse response (FIR) has a controller which reads parallel sample data out of an FFT memory in such a manner as to generate an even function, the sample data applied to a preamble equalizer accompanied by a preamble sign and zero, the preamble outputs coupled to three filter processors, each filter processor having four filter engines whose outputs are summed, the channel smoothing filter generating an a register output, the register input coupled to a summer which has as inputs: the first filter processor shifted by four, the second filter processor shifted by two, the third filter processor, and the register output. Coefficients for an edge filter and a central filter are provided in Zero Sign Shift (ZSS) format, and by selection of coefficients using a canonical signed digit (CSD) algorithm, no multipliers are required for the channel smoothing FIR filter.

    摘要翻译： 具有有限脉冲响应（FIR）的信道平滑滤波器具有控制器，其以这样的方式从FFT存储器中读取并行取样数据，以产生偶函数，该样本数据应用于伴有前置码符号的前同步码均衡器， 零，所述前导码输出耦合到三个滤波器处理器，每个滤波器处理器具有四个滤波器引擎，其输出相加，所述信道平滑滤波器产生寄存器输出，耦合到具有作为输入的加法器的寄存器输入：第一滤波器处理器被移位 由四个，第二个滤波器处理器移位两个，第三个滤波器处理器和寄存器输出。 边缘滤波器和中央滤波器的系数以零符号移位（ZSS）格式提供，并且通过使用规范有符号数字（CSD）算法选择系数，通道平滑FIR滤波器不需要乘法器。

    Channel Estimation Filter for OFDM receiver
    8.
    发明申请
    Channel Estimation Filter for OFDM receiver 有权
    OFDM接收机的信道估计滤波器

    公开(公告)号：US20100202504A1

    公开(公告)日：2010-08-12

    申请号：US12368431

    申请日：2009-02-10

    申请人： Partha Sarathy Murali ,  Kashiviswanath Nethi ,  Karthik Vaidyanathan ,  Sundaram Vanka

    发明人： Partha Sarathy Murali ,  Kashiviswanath Nethi ,  Karthik Vaidyanathan ,  Sundaram Vanka

    IPC分类号： H03K5/159

    CPC分类号： H04L27/2647 ,  H04L25/022 ,  H04L25/03159

    摘要： A channel smoothing filter with a finite impulse response (FIR) has a controller which reads parallel sample data out of an FFT memory in such a manner as to generate an even function, the sample data applied to a preamble equalizer accompanied by a preamble sign and zero, the preamble outputs coupled to three filter processors, each filter processor having four filter engines whose outputs are summed, the channel smoothing filter generating an a register output, the register input coupled to a summer which has as inputs: the first filter processor shifted by four, the second filter processor shifted by two, the third filter processor, and the register output. Coefficients for an edge filter and a central filter are provided in Zero Sign Shift (ZSS) format, and by selection of coefficients using a canonical signed digit (CSD) algorithm, no multipliers are required for the channel smoothing FIR filter.

    摘要翻译： 具有有限脉冲响应（FIR）的信道平滑滤波器具有控制器，其以这样的方式从FFT存储器中读取并行取样数据，以产生偶函数，该样本数据应用于伴有前置码符号的前同步码均衡器， 零，所述前导码输出耦合到三个滤波器处理器，每个滤波器处理器具有四个滤波器引擎，其输出相加，所述信道平滑滤波器产生寄存器输出，耦合到具有作为输入的加法器的寄存器输入：第一滤波器处理器被移位 由四个，第二个滤波器处理器移位两个，第三个滤波器处理器和寄存器输出。 边缘滤波器和中央滤波器的系数以零符号移位（ZSS）格式提供，并且通过使用规范有符号数字（CSD）算法选择系数，通道平滑FIR滤波器不需要乘法器。

    Reed-solomon decoder using a configurable arithmetic processor
    9.
    发明授权
    Reed-solomon decoder using a configurable arithmetic processor 有权
    Reed-solomon解码器使用可配置的算术处理器

    公开(公告)号：US07870468B1

    公开(公告)日：2011-01-11

    申请号：US11441596

    申请日：2006-05-26

    申请人： Sundaram Vanka ,  Phanimithra Gangalakurthi

    发明人： Sundaram Vanka ,  Phanimithra Gangalakurthi

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1545 ,  H03M13/1515 ,  H03M13/1525 ,  H03M13/154 ,  H03M13/155 ,  H03M13/618 ,  H03M13/6362

    摘要： A Reed Solomon decoder utilizes re-configurable and re-usable components in a granular configuration which provides an upper array and a lower array of repeated Reconfigurable Elementary Units (REU) which in conjunction with a FIFO can be loaded with syndromes and correction terms to decode Reed Solomon codewords. The upper array of REUs and lower array of REUs handle the Reed Solomon decoding steps in a pipelined manner using systolic REU structures. The repeated REU includes the two registers, two Galois Field adders, a Galois Field multiplier, and multiplexers to interconnect the elements. The REU is then able to perform each of the steps required for Reed-Solomon decoder through reconfiguration for each step using the multiplexers to reconfigure the functions. In this manner, a reconfigurable computational element may be used for each step of the Reed-Solomon decoding process.

    摘要翻译： Reed Solomon解码器采用粒度配置中的可重新配置和可重复使用的组件，其提供重复可重配置单元（REU）的上阵列和下阵列，其结合FIFO可以加载校正子和校正项来解码 里德所罗门码字。 REU的上排列和REU的较低阵列使用收缩式REU结构以流水线方式处理Reed Solomon解码步骤。 重复的REU包括两个寄存器，两个Galois Field加法器，Galois Field乘法器和用于互连元件的多路复用器。 然后，REU能够通过使用多路复用器重新配置功能的每个步骤通过重新配置来执行Reed-Solomon解码器所需的每个步骤。 以这种方式，可以对Reed-Solomon解码处理的每个步骤使用可重新配置的计算元件。