公开(公告)号：US20050193253A1

公开(公告)日：2005-09-01

申请号：US10708184

申请日：2004-02-13

申请人： Jonathan Fales ,  Gregory Fredeman ,  Kevin Gorman ,  Mark Jacunski ,  Toshiaki Kirihata ,  Alan Norris ,  Paul Parries ,  Matthew Wordeman

发明人： Jonathan Fales ,  Gregory Fredeman ,  Kevin Gorman ,  Mark Jacunski ,  Toshiaki Kirihata ,  Alan Norris ,  Paul Parries ,  Matthew Wordeman

IPC分类号： G06F11/00 ,  G11C29/14 ,  G11C29/16

CPC分类号： G11C29/16 ,  G11C29/12015 ,  G11C29/14 ,  G11C2029/0401

摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.

摘要翻译： 公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。 命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。

公开(公告)号：US20050180230A1

公开(公告)日：2005-08-18

申请号：US10777596

申请日：2004-02-12

申请人： Gregory Fredeman ,  Mark Jacunski ,  Toshiaki Kirihata ,  Matthew Wordeman

发明人： Gregory Fredeman ,  Mark Jacunski ,  Toshiaki Kirihata ,  Matthew Wordeman

IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C29/40 ,  G11C29/44

CPC分类号： G11C29/4401 ,  G11C29/40 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/0401 ,  G11C2029/2602

摘要： A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.

摘要翻译： 描述了在包括两个或更多个冗余域的存储器设备中在多存储体操作期间分配冗余的方法。 该方法包括启用通过/故障位检测来激活给定的存储体的步骤。 通过/失败位检测仅对选定的域提示，并且在寻址其他域时被禁用。 通过改变域选择，无论多行操作如何，都可以为任何域启用冗余分配。 该方法可以优选地通过使用具有真实和补充预期数据对的动态异或逻辑来实现。 当结合简单的指针逻辑时，可以内部生成域的选择，简化内置的自检和其他测试控制协议，同时跟踪失败的那些。

公开(公告)号：US06674673B1

公开(公告)日：2004-01-06

申请号：US10064867

申请日：2002-08-26

申请人： Louis Lu-Chen Hsu ,  Gregory Fredeman ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Dale E. Pontius

发明人： Louis Lu-Chen Hsu ,  Gregory Fredeman ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Dale E. Pontius

IPC分类号： G11C700

CPC分类号： G11C29/846 ,  G11C2207/104

摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.

公开(公告)号：US20080030260A1

公开(公告)日：2008-02-07

申请号：US11872273

申请日：2007-10-15

申请人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

发明人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

IPC分类号： H01H37/76

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构包括用于感测可编程电阻性存储元件装置的状态的装置，该装置还包括耦合到熔丝节点和参考节点的锁存装置，所述熔丝节点包括 所述锁存装置被配置为检测在所述参考节点和所述熔丝节点之间产生的差动信号，这是由于感测电流通过所述保险丝腿和所述参考电阻腿的结果; 并且熔丝和参考电阻腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流电平。

公开(公告)号：US20080025071A1

公开(公告)日：2008-01-31

申请号：US11868046

申请日：2007-10-05

申请人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

发明人： Darren Anand ,  Gregory Fredeman ,  Toshiaki Kirihata ,  Alan Leslie ,  John Safran

IPC分类号： G11C11/00

CPC分类号： G11C7/065 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027

摘要： A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse node of the test circuit as a result of the first level of current; passing a second level of current through the fuse leg and the reference leg of a test circuit, the second level of current being higher than the first level of current so as to enable detection of trip resistance of the test circuit at a lower value than with respect to the first level of current; and detecting a differential signal developed between the reference node and the fuse node of the test circuit as a result of the second level of current.

摘要翻译： 用于确定可编程电阻性存储元件的状态的方法包括使第一电平电流通过包括可编程电阻存储器元件的测试电路的熔丝支脚和参考电阻支路; 检测作为第一电流电平的结果，在测试电路的参考节点和熔丝节点之间产生的差分信号; 使第二电流通过保险丝支脚和测试电路的参考支路，第二电平电流高于第一电流电平，以便能够以比与第一电平相比更低的值检测测试电路的跳闸电阻 尊重目前的一级; 以及作为所述第二电流电平的结果，检测在所述参考节点和所述测试电路的所述熔丝节点之间产生的差分信号。

公开(公告)号：US20050122801A1

公开(公告)日：2005-06-09

申请号：US11031138

申请日：2005-01-07

申请人： Louis Hsu ,  Gregory Fredeman ,  Rajiv Joshi ,  Toshiaki Kirihata

发明人： Louis Hsu ,  Gregory Fredeman ,  Rajiv Joshi ,  Toshiaki Kirihata

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808

摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size. Furthermore, a method is provided for replacing faulty wordlines of a memory array including the steps of: selecting a repair field size; storing at least one faulty address into a first memory; and copying the stored at least one faulty address from the first memory into a variable number of storage cells of a second memory, wherein each storage cell of said second memory corresponds to a respective bank of said plurality of banks; and wherein the variable number of storage cells is in accordance with the selected repair field size.

摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。 此外，提供了一种用于替换存储器阵列的错误字线的方法，包括以下步骤：选择修复字段大小; 将至少一个故障地址存储到第一存储器中; 以及将存储的至少一个故障地址从第一存储器复制到第二存储器的可变数量的存储单元中，其中所述第二存储器的每个存储单元对应于所述多个存储体的相应存储体; 并且其中所述可变数量的存储单元符合所选择的修复字段大小。

公开(公告)号：US20050013185A1

公开(公告)日：2005-01-20

申请号：US10604375

申请日：2003-07-15

申请人： Hoki Kim ,  Toshiaki Kirihata ,  David Hanson ,  Gregory Fredeman ,  John Golz

发明人： Hoki Kim ,  Toshiaki Kirihata ,  David Hanson ,  Gregory Fredeman ,  John Golz

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

摘要翻译： 在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。 每个组的比较器提供一个比较器输出。 每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。 仲裁器被连接以接收信号中的冲突并提供冲突信号。 一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。

公开(公告)号：US06674676B1

公开(公告)日：2004-01-06

申请号：US10444226

申请日：2003-05-23

申请人： Louis Lu-Chen Hsu ,  Gregory Fredeman ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Dale E. Pontius

发明人： Louis Lu-Chen Hsu ,  Gregory Fredeman ,  Chorng-Lii Hwang ,  Toshiaki Kirihata ,  Dale E. Pontius

IPC分类号： G11C700

CPC分类号： G11C29/846 ,  G11C2207/104

摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.

摘要翻译： 一种列冗余系统，包括用于执行各个微单元内的列元素的冗余交换操作的列冗余设备。 列冗余装置还包括熔丝信息存储装置，第一存储体地址解码机构对与读取操作相关的第一微小区对应的读存储体地址进行解码，第二存储体地址解码机构对与 访问用于写操作的第二微小区。 如果存在包含在第一微单元内的至少一个有缺陷的列元素，则列冗余设备生成与第一微单元中的至少一个缺陷列元素对应的内部列地址。 类似地，如果在第二微小区内包含至少一个有缺陷的列元素，则列冗余设备产生对应于第二微小区中的至少一个缺陷列元素的内部列地址。

公开(公告)号：US06990025B2

公开(公告)日：2006-01-24

申请号：US10604994

申请日：2003-08-29

申请人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

发明人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

IPC分类号： G11C7/00

CPC分类号： G11C11/405 ,  G11C8/16 ,  G11C11/4099

摘要： A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors. For a given sense amplifier and its associated RBLs, the coupling creates an identical coupling noise on RBLA and RBLB that are positioned in the two arrays A and B. This common mode noise is rejected by the differential sense amplifier. Thus, a read sense amplifier can accurately discriminate between the signal by activating the cell by way of RWL, and the reference cell by way of REFWL.

摘要翻译： 描述了利用读取位线的开放位线配置的多端口存储器架构。 存储器被细分为由矩阵形式排列的存储器增益单元组成的两个阵列（A和B），这些单元具有两个通用端口或单独的读取和写入端口，以实现读写操作。 每个存储器阵列包括耦合到参考单元的参考字线。 当参考单元被访问时，读位线（RBL）放电到由存储0或1的单元取得的值的一半的电平上。两个阵列的同一列中的每对RBLB耦合到差分读出放大器 ，并且两个阵列中的每个写入位线（WBL）链接到写入驱动器，两个阵列中的WBLs被驱动到相同的电压和相同的转换速率。 每个阵列中的WBL摆幅通过位线到位线电容产生耦合噪声。 对于给定的读出放大器及其相关联的RBL，耦合在位于两个阵列A和B中的RBLA和RBLB上产生相同的耦合噪声。这种共模噪声被差分读出放大器拒绝。 因此，读出读出放大器可以通过RWL通过激活单元以及通过REFWL来使参考单元精确地区分信号。

公开(公告)号：US20050047218A1

公开(公告)日：2005-03-03

申请号：US10604994

申请日：2003-08-29

申请人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

发明人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

IPC分类号： G11C5/00 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4099

CPC分类号： G11C11/405 ,  G11C8/16 ,  G11C11/4099

摘要： A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors. For a given sense amplifier and its associated RBLs, the coupling creates an identical coupling noise on RBLA and RBLB that are positioned in the two arrays A and B. This common mode noise is rejected by the differential sense amplifier. Thus, a read sense amplifier can accurately discriminate between the signal by activating the cell by way of RWL, and the reference cell by way of REFWL.

摘要翻译： 描述了利用读取位线的开放位线配置的多端口存储器架构。 存储器被细分为由矩阵形式排列的存储器增益单元组成的两个阵列（A和B），这些单元具有两个通用端口或单独的读取和写入端口，以实现读写操作。 每个存储器阵列包括耦合到参考单元的参考字线。 当参考单元被访问时，读位线（RBL）放电到由存储0或1的单元取得的值的一半的电平上。两个阵列的同一列中的每对RBLB耦合到差分读出放大器 ，并且两个阵列中的每个写入位线（WBL）链接到写入驱动器，两个阵列中的WBLs被驱动到相同的电压和相同的转换速率。 每个阵列中的WBL摆幅通过位线到位线电容产生耦合噪声。 对于给定的读出放大器及其相关联的RBL，耦合在位于两个阵列A和B中的RBLA和RBLB上产生相同的耦合噪声。这种共模噪声被差分读出放大器拒绝。 因此，读出读出放大器可以通过RWL通过激活单元以及通过REFWL来使参考单元精确地区分信号。