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公开(公告)号：US07257043B2
公开(公告)日：2007-08-14
申请号：US11358234
申请日：2006-02-21
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C11/401 , G11C11/4097 , G11C29/816 , G11C2207/002 , G11C2207/005 , Y10S257/906
摘要： A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.
摘要翻译： 存储器件包括位于存储器单元之间的隔离器件。 多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。 在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。
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公开(公告)号：US06834019B2
公开(公告)日：2004-12-21
申请号：US10233325
申请日：2002-08-29
IPC分类号： G11C700
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C11/401 , G11C11/4097 , G11C29/816 , G11C2207/002 , G11C2207/005 , Y10S257/906
摘要： A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.
摘要翻译： 存储器件包括位于存储器单元之间的隔离器件。 多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。 在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。
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公开(公告)号：US07020039B2
公开(公告)日：2006-03-28
申请号：US10998483
申请日：2004-11-29
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C11/401 , G11C11/4097 , G11C29/816 , G11C2207/002 , G11C2207/005 , Y10S257/906
摘要： A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.
摘要翻译： 存储器件包括位于存储器单元之间的隔离器件。 多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。 在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。
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公开(公告)号：US07245548B2
公开(公告)日：2007-07-17
申请号：US10900246
申请日：2004-07-27
申请人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
发明人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C11/4085
摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
摘要翻译： 利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。 更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。 如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。 如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。
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公开(公告)号：US06717873B2
公开(公告)日：2004-04-06
申请号：US10317106
申请日：2002-12-12
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C11/4091
摘要： A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.
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公开(公告)号：US07746720B2
公开(公告)日：2010-06-29
申请号：US11879396
申请日：2007-07-17
申请人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
发明人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
IPC分类号： G11C8/00
CPC分类号： G11C11/412 , G11C11/4085
摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
摘要翻译： 利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。 更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。 如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。 如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。
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7.发明授权Apparatus and method to reduce undesirable effects caused by a fault in a memory device 有权用于减少由存储器件中的故障引起的不期望的影响的装置和方法公开(公告)号：US07336522B2
公开(公告)日：2008-02-26
申请号：US11489119
申请日：2006-07-19
IPC分类号： G11C11/24
CPC分类号： G11C7/12 , G11C7/02 , G11C7/1048 , G11C11/4085 , G11C11/4094 , G11C11/4096 , G11C2207/002
摘要： A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.
摘要翻译： 提供了一种减少存储器件中的电流的方法和装置。 外围设备控制信号被转换为字线关断电压电平，例如负字线电压。 转换后的信号可防止外围设备在字线关闭模式下传导电流，即使发生字线数字短路。 控制信号可以包括列选择装置的列选择信号和用于感测放大器的有源上拉信号等。 此外，为存储器件提供具有高电阻和低电阻分量的均衡电路。 均衡电路限制电流，即使发生字线数字短路。
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公开(公告)号：US07142446B2
公开(公告)日：2006-11-28
申请号：US10902728
申请日：2004-07-29
IPC分类号： G11C11/24
CPC分类号： G11C7/12 , G11C7/02 , G11C7/1048 , G11C11/4085 , G11C11/4094 , G11C11/4096 , G11C2207/002
摘要： A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.
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公开(公告)号：US06816425B2
公开(公告)日：2004-11-09
申请号：US10775231
申请日：2004-02-11
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C11/4091
摘要： A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.
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公开(公告)号：US06515925B2
公开(公告)日：2003-02-04
申请号：US09805933
申请日：2001-03-15
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C11/4091
摘要： A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.
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