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1.发明授权Processor and method of grouping and executing dependent instructions in a packet 有权分组和执行分组中的相关指令的处理器和方法公开(公告)号：US07523295B2
公开(公告)日：2009-04-21
申请号：US11086475
申请日：2005-03-21
CPC分类号： G06F9/3885 , G06F9/3851 , G06F9/3853
摘要： An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.
摘要翻译： 交错多线程流水线操作方法包括读取包含至少两个指令的指令分组，将指令分组的第一指令转向第一执行单元以执行并产生第一结果，将指令分组的第二指令转向第二执行 使用第一结果执行的单元并产生第二结果，并存储第二结果。
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2.发明授权Controlling execution mode of program threads by applying a mask to a control register in a multi-threaded processor 有权通过对多线程处理器中的控制寄存器应用掩码来控制程序线程的执行模式公开(公告)号：US07849466B2
公开(公告)日：2010-12-07
申请号：US11180017
申请日：2005-07-12
申请人： Lucian Codrescu , Donald Robert Padgett , Erich Plondke , Taylor Simpson , Muhammad Ahmed , William C. Anderson , Sujat Jamil
发明人： Lucian Codrescu , Donald Robert Padgett , Erich Plondke , Taylor Simpson , Muhammad Ahmed , William C. Anderson , Sujat Jamil
CPC分类号： G06F9/3851 , G06F1/3228 , G06F1/3243 , G06F9/30181 , G06F9/30189 , G06F9/3853 , G06F9/4843 , Y02D10/152 , Y02D10/24
摘要： A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program threads and a second data field to control a second execution mode of a second of the plurality of executable program threads. In a particular embodiment, the first execution mode is a run mode and the second execution mode is a low power mode.
摘要翻译： 公开了一种多线程处理器设备，并且包括被配置为执行多个可执行程序线程和模式控制寄存器的处理器。 模式控制寄存器包括用于控制多个可执行程序线程中的第一个的第一执行模式的第一数据字段和用于控制多个可执行程序线程中的第二个可执行程序线程的第二执行模式的第二数据字段。 在特定实施例中，第一执行模式是运行模式，第二执行模式是低功率模式。
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3.发明授权Method and system for variable thread allocation and switching in a multithreaded processor 有权多线程处理器中可变线程分配和切换的方法和系统公开(公告)号：US07917907B2
公开(公告)日：2011-03-29
申请号：US11089474
申请日：2005-03-23
CPC分类号： G06F9/3851
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.
摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。 多线程处理器经由多个处理器管线处理多个线程。 该方法包括确定多线程处理器工作的工作频率F的步骤。 然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。 可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化 操作多线程处理器。 在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。
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4.发明授权System and method of executing program threads in a multi-threaded processor 有权在多线程处理器中执行程序线程的系统和方法公开(公告)号：US07814487B2
公开(公告)日：2010-10-12
申请号：US11115917
申请日：2005-04-26
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A multithreaded processor device is disclosed and includes a first program thread and second program thread. The second program thread is execution linked to the first program thread in a lock step manner. As such, when the first program thread experiences a stall event, the second program thread is instructed to perform a no operation instruction in order to keep the second program thread execution linked to the first program thread. Also, the second program thread performs a no operation instruction during each clock cycle that the first program thread is stalled due to the stall event. When the first program thread performs a first successful operation after the stall event, the second program thread restarts normal execution.
摘要翻译： 公开了一种多线程处理器设备，并且包括第一程序线程和第二程序线程。 第二个程序线程以锁定步骤的方式执行链接到第一个程序线程。 这样，当第一程序线程经历停顿事件时，指示第二程序线程执行无操作指令，以便使第二程序线程执行与第一程序线程相关联。 此外，第二程序线程在每个时钟周期期间执行无操作指令，由于失速事件使第一程序线程停滞。 当第一程序线程在停止事件之后执行第一次成功操作时，第二程序线程重新启动正常执行。
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5.发明授权Method and system for encoding variable length packets with variable instruction sizes 有权用可变指令大小编码可变长度数据包的方法和系统公开(公告)号：US07526633B2
公开(公告)日：2009-04-28
申请号：US11088607
申请日：2005-03-23
CPC分类号： G06F9/30149 , G06F9/3853
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of instructions of a second length. The method and system encode a header having at least one instruction length bit. The instruction bit distinguishes between instructions of the first length and instructions of the second length for an associated DSP to process in a mixed stream. The method and system distinguish between the instructions of the first length and the instructions of the second length according to the contents of the instruction length bits. The header further includes bits for distinguishing between instructions of varying lengths in an instruction packet.
摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 该方法和系统编码和处理混合长度（例如，16位和32位）的指令以及包括混合长度指令的指令包。 这包括编码第一长度的多个指令和第二长度的多个指令。 该方法和系统对具有至少一个指令长度位的报头进行编码。 指令位区分第一长度的指令和第二长度的指令，以使相关的DSP在混合流中进行处理。 方法和系统根据指令长度位的内容区分第一长度的指令和第二长度的指令。 标题还包括用于区分指令包中不同长度的指令的位。
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公开(公告)号：US07383420B2
公开(公告)日：2008-06-03
申请号：US11089619
申请日：2005-03-24
CPC分类号： G06F9/35 , G06F9/3851 , G06F9/3853
摘要： A processor is operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the first register-out value and obtaining a second register-out value, and storing the second register-out value into a third register based on the program instruction. The processor is further operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the program instruction and obtaining a second register-out value, and storing the first register-out value into a third register based on the second register-out value.
摘要翻译： 处理器可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于第一寄存器输出值访问第二寄存器并获得第二寄存器值， 以及基于所述程序指令将所述第二寄存器值存储到第三寄存器中。 处理器还可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于所述程序指令访问第二寄存器并获得第二寄存器值，以及存储 基于第二寄存器值将第一寄存器值输入到第三寄存器中。
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7.发明授权Mixed superscalar and VLIW instruction issuing and processing method and system 有权混合超标量和VLIW指令发布和处理方法和系统公开(公告)号：US07590824B2
公开(公告)日：2009-09-15
申请号：US11093375
申请日：2005-03-29
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e.g., VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e.g., superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction's relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.
摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 用于在多问题数字信号处理器中发出和执行混合架构指令的方法和系统以列出多个数字信号处理器指令的混合指令接收。 多个数字信号处理器指令包括在多个串行可执行指令（例如，超标量指令）中混合的多个并行可执行指令（例如，VLIW指令或指令分组）。 该系列可执行指令通过各种指令依赖关联。 该方法和系统进一步标识列出多个并行可执行指令的混合指令。 一旦确定，并行执行并行执行指令，而不管混合指令列表中的这种指令的相对顺序如何。 然后，根据所述各种指令依赖性，串行执行指令被串行执行。
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8.发明授权Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权为交错多线程环境中的数字信号处理器注册文件公开(公告)号：US08713286B2
公开(公告)日：2014-04-29
申请号：US11115916
申请日：2005-04-26
IPC分类号： G06F7/57
CPC分类号： G06F9/30149 , G06F9/3012 , G06F9/3851 , G06F9/3885
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.
摘要翻译： 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。 处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。
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公开(公告)号：US07685411B2
公开(公告)日：2010-03-23
申请号：US11104115
申请日：2005-04-11
申请人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William C. Anderson , Robert Allan Lester , Phillip M. Jones
发明人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William C. Anderson , Robert Allan Lester , Phillip M. Jones
IPC分类号： G06F9/00
CPC分类号： G06F9/325 , G06F9/3802 , G06F9/3804 , G06F9/381
摘要： An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.
摘要翻译： 指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。 如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。 第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从 如果目标指令没有存储在第二存储器结构中的第一存储器结构。
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公开(公告)号：US07398371B2
公开(公告)日：2008-07-08
申请号：US11165757
申请日：2005-06-23
CPC分类号： G06F9/4812 , G06F12/1027 , Y02D10/13 , Y02D10/24
摘要： A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.
摘要翻译： 共享翻译后备缓冲方法包括：当遇到异常/中断时，将存储在第一选定寄存器组中的数据保存到存储器中线程特定区域的预定部分，重新启用异常和可选中断，解决原因 异常/中断，同时安全地允许另一个异常，并将保存的数据恢复到第一选定的寄存器组。
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