公开(公告)号：US5532972A

公开(公告)日：1996-07-02

申请号：US391920

申请日：1995-02-21

申请人： Luigi Pascucci ,  Silvia Padoan ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

发明人： Luigi Pascucci ,  Silvia Padoan ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C16/32 ,  G11C7/1006 ,  G11C7/22

摘要： A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.

摘要翻译： 电路包括产生用于异步地使读取相位的脉冲信号的部分; 产生预充电和检测可调节持续时间的信号的部分，用于控制从存储器读取数据并向输出缓冲器提供数据; 产生用于在加载到输出电路期间将输出缓冲器中的数据冻结的噪声抑制信号的部分，其持续时间恰好等于数据到存储器的输出电路的传播时间，如通过传播 输出仿真电路中的数据模拟信号; 产生负载信号的部分，其持续时间可以等于噪声抑制信号的延迟，或者在阵列呈现较慢的元素，由此可以被读取的情况下由扩展电路扩展; 以及产生电路复位信号的部分。

公开(公告)号：US5541884A

公开(公告)日：1996-07-30

申请号：US391147

申请日：1995-02-21

申请人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

发明人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32 ,  G11C17/00

CPC分类号： G11C7/02 ,  G11C16/32 ,  G11C7/1006 ,  G11C7/22

摘要： In a nonvolatile memory comprising a data amplifying unit and an output element mutually connected by a connection line, the noise suppressing circuit comprises a network for generating a noise suppressing signal which is synchronized substantially perfectly with a signal controlling data loading from the amplifying unit to the output unit, presents a very short duration, equal to the switching time of the output unit, and freezes the amplifying unit during switching of the output unit to prevent this from altering the data stored in the amplifying unit or internal circuits of the memory. The same signal also blocks an address amplifying unit on the address bus.

摘要翻译： 在包括数据放大单元和通过连接线相互连接的输出元件的非易失性存储器中，噪声抑制电路包括用于产生噪声抑制信号的网络，该噪声抑制信号与控制从放大单元加载到 输出单元呈现相当于输出单元的切换时间的非常短的持续时间，并且在切换输出单元期间使放大单元冻结，以防止其改变存储在放大单元中的数据或存储器的内部电路。 相同的信号也阻塞地址总线上的地址放大单元。

公开(公告)号：US5563826A

公开(公告)日：1996-10-08

申请号：US422813

申请日：1995-04-17

申请人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone

发明人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/24 ,  G11C16/28 ,  G11C7/06

CPC分类号： G11C16/28 ,  G11C16/24

摘要： A read circuit comprises at least one array branch connected to at least one bit line, and a reference branch connected to a reference line. The array and reference branches each comprise a precharge circuit and load interposed between the supply and the bit line and reference line respectively. The reference load is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line. The reference line is connected to an extra-current transistor which is only turned on during equalization so that, during equalization, the selected bit line is supplied with a high current approximating that supplied to the reference line. As such, if the cell to be read is written, the output voltage of the array branch is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.

摘要翻译： 读取电路包括连接到至少一个位线的至少一个阵列分支和连接到参考线的参考分支。 阵列和参考支路各自包括预充电电路和插入在电源和位线和参考线之间的负载。 参考负载被形成为产生参考电流，其在评估期间是提供给位线的电流的两倍。 参考线连接到在均衡期间仅导通的过电流晶体管，使得在均衡期间，所选择的位线被提供近似于提供给参考线的高电流。 因此，如果要读取的单元被写入，则阵列分支的输出电压迅速地达到其自然的高值; 而如果要读取的单元被擦除，则当超级晶体管截止时，输出电压可能返回到其低电平值，因此可以预先读取。

公开(公告)号：US5499217A

公开(公告)日：1996-03-12

申请号：US348461

申请日：1994-12-02

申请人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone

发明人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone

IPC分类号： G11C17/00 ,  G11C8/10 ,  G11C16/06 ,  G11C8/00

CPC分类号： G11C8/10

摘要： A memory line decoding driver is so biased that the P channel pull-up transistor biasing the final inverter conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage alternatively connects the gate terminal of the pull-up transistor to a capacitor, with which the charge is distributed, and to the supply.

摘要翻译： 存储器线路解码驱动器被偏置，使得偏置最终的反相器的P沟道上拉晶体管在线路地址瞬态阶段期间导通高电流，以便对最终的反相器的输入进行快速充电，并且在静态期间弱 在一个地址阶段和另一个之间，以减少电流消耗。 为此，电压调制级将上拉晶体管的栅极端子交替地连接到电荷分配的电容器和电源。

公开(公告)号：US5650671A

公开(公告)日：1997-07-22

申请号：US379689

申请日：1995-01-27

申请人： Luigi Pascucci ,  Marco Maccarrone ,  Silvia Padoan

发明人： Luigi Pascucci ,  Marco Maccarrone ,  Silvia Padoan

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H02M3/07 ,  H02M3/18

CPC分类号： H02M3/07 ,  G11C5/145

摘要： A charge pump circuit including a number of pull-up stages connected in parallel with one another between a reference potential line and an output line. Each stage includes a capacitor having a first terminal connected to a charging and discharging node, and a second terminal connected to a pull-up node for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node is connected to the supply line via a charging transistor having a control terminal connected to a high-voltage bias node formed by the adjacent stage in the opposite operating phase, for charging the capacitor substantially up to the supply voltage.

摘要翻译： 一种电荷泵电路，包括在参考电位线和输出线之间彼此并联连接的多个上拉级。 每个级包括具有连接到充电和放电节点的第一端子的电容器，以及连接到上拉节点的第二端子，用于在第一充电操作阶段和第二充电转移操作阶段之间切换。 充电和放电节点通过充电晶体管连接到电源线，该充电晶体管具有在相反的工作阶段中由相邻级形成的高压偏置节点连接的控制端子，用于对电容器充电至基本上达到电源电压。

公开(公告)号：US5548554A

公开(公告)日：1996-08-20

申请号：US365154

申请日：1994-12-28

申请人： Luigi Pascucci ,  Silvia Padoan ,  Marco Maccarrone

发明人： Luigi Pascucci ,  Silvia Padoan ,  Marco Maccarrone

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/70

摘要： An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits, each one associated with a respective memory matrix portion or group of columns, and a plurality of programming load control circuits, each one controlling the activation of one respective programming load circuit according to the logic state of a respective data line carrying a datum to be programmed; the memory device comprises a group of redundancy bit lines and an associated redundancy programming load circuit; each programming load control circuit comprises decoding means supplied with signals which, when a defective column address is supplied to the memory device during programming, are generated from a matrix portion identifying code stored in a non-volatile register wherein the defective column address is stored, and switch means responsive to a decoded signal at the output of said decoding means to enable the activation of the redundancy programming load circuit according to the logic state of the data signal line and to cause the inhibition of the activation of the respective programming load circuit.

摘要翻译： 用于电可编程半导体存储器件的集成编程电路包括多个编程负载电路，每个编程负载电路各自与相应的存储器矩阵部分或一组列相关联，以及多个编程负载控制电路，每个编程负载控制电路控制一个相应的激活 根据携带要编程的数据的相应数据线的逻辑状态编程负载电路; 存储器件包括一组冗余位线和相关的冗余编程负载电路; 每个编程负载控制电路包括提供有信号的解码装置，当在编程期间将缺陷列地址提供给存储器件时，从存储在存储有缺陷列地址的非易失性寄存器中的矩阵部分识别代码生成信号， 以及响应于所述解码装置的输出处的解码信号的开关装置，以使能根据数据信号线的逻辑状态激活冗余编程负载电路，并且导致禁止各个编程负载电路的激活。

公开(公告)号：US5515332A

公开(公告)日：1996-05-07

申请号：US391160

申请日：1995-02-21

申请人： Luigi Pascucci ,  Marco Maccarrone ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Maccarrone ,  Marco Olivo

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32

CPC分类号： G11C7/02 ,  G11C16/32 ,  G11C7/1006 ,  G11C7/22

摘要： A load timing circuit including an output simulation circuit similar to the output circuits of the memory, so as to present the same propagation delay; a simulating signal source for generating a data simulating signal; a synchronizing network for detecting a predetermined switching edge of the data simulating signal and enabling supply of the signal to the output simulation circuit and data supply to the output circuits of the memory; a combinatorial network for detecting propagation of the data simulating signal to the output of the output simulation circuit and disabling the data simulating signal; and a reset element for resetting the timing circuit.

摘要翻译： 一种负载定时电路，包括与存储器的输出电路相似的输出模拟电路，以便呈现相同的传播延迟; 用于产生数据模拟信号的模拟信号源; 同步网络，用于检测数据模拟信号的预定切换边沿，并且能够向输出模拟电路提供信号，并向存储器的输出电路提供数据; 组合网络，用于检测数据模拟信号的传播到输出模拟电路的输出，并禁用数据模拟信号; 以及用于复位定时电路的复位元件。

公开(公告)号：US5566114A

公开(公告)日：1996-10-15

申请号：US349783

申请日：1994-12-06

申请人： Luigi Pascucci ,  Carla M. Golla

发明人： Luigi Pascucci ,  Carla M. Golla

IPC分类号： H01L21/82 ,  G11C29/00 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C29/70

摘要： A redundancy circuitry for a semiconductor memory device comprising a matrix of memory elements and a plurality of programmable non-volatile memory registers. The non-volatile memory registers being programmable to store addresses of defective memory elements that must be replaced by redundancy memory elements. The redundancy circuitry comprises a combinatorial circuit supplied by address signals and supplying the non-volatile registers with an inhibition signal for inhibiting the selection of redundancy memory elements when a memory element of the matrix is addressed whose address coincides with the address stored in a non-programmed memory register.

摘要翻译： 一种用于半导体存储器件的冗余电路，包括存储元件矩阵和多个可编程非易失性存储寄存器。 非易失性存储器寄存器是可编程的，以存储必须由冗余存储器元件替代的缺陷存储器元件的地址。 冗余电路包括由地址信号提供的组合电路，并且当矩阵的存储元件被寻址时，向非易失性寄存器提供用于禁止冗余存储器元件的选择的禁止信号，其地址与存储在非易失性寄存器中的地址一致， 程序存储器寄存器。

公开(公告)号：US5644529A

公开(公告)日：1997-07-01

申请号：US635455

申请日：1996-04-18

申请人： Luigi Pascucci ,  Silvia Padoan

发明人： Luigi Pascucci ,  Silvia Padoan

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C11/40

CPC分类号： G11C29/789 ,  G11C16/12 ,  G11C29/12

摘要： In an integrated circuit for programming a memory cell in a non-volatile memory register which is associated with a memory matrix wherein the non-volatile memory register is used to store a redundancy address, the memory cell has at least one programmable non-volatile memory element having a control electrode and a data electrode and is suitable to store one bit of information. A load circuit associated to the memory element reads the information stored therein. The integrated circuit has switching means connected in series between the data electrode and a respective address signal line of an address signal bus which also supplies a decoding circuitry of the memory matrix. The switching means are controlled by a signal which determines the switching means to electrically connect the data electrode of the memory element to the address signal line when the memory cell of the non-volatile memory register is to be programmed, and to electrically disconnect the data electrode of the memory element from the address signal line when the information stored in the memory element is to be read by the load circuit.

摘要翻译： 在用于对与非易失性存储器寄存器用于存储冗余地址的存储器矩阵相关联的非易失性存储器寄存器中的存储器单元进行编程的集成电路中，存储器单元具有至少一个可编程非易失性存储器 元件具有控制电极和数据电极，并且适合于存储一位信息。 与存储器元件相关联的负载电路读取存储在其中的信息。 集成电路具有串联连接在数据电极和还提供存储器矩阵的解码电路的地址信号总线的相应地址信号线之间的开关装置。 开关装置由确定开关装置的信号控制，当非易失性存储寄存器的存储单元要被编程时，切换装置将存储元件的数据电极电连接到地址信号线，并且电连接数据 当存储在存储元件中的信息要由负载电路读取时，来自地址信号线的存储元件的电极。

公开(公告)号：US5687124A

公开(公告)日：1997-11-11

申请号：US521304

申请日：1995-08-30

申请人： Carla Golla ,  Silvia Padoan ,  Luigi Pascucci

发明人： Carla Golla ,  Silvia Padoan ,  Luigi Pascucci

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C16/02 ,  G11C16/34

CPC分类号： G11C16/3486 ,  G11C16/3459 ,  G11C16/3468

摘要： A circuit for selectively programming a single bit in non-volatile memory is disclosed. The circuit consists of at least one comparator, at least one transistor, and at least one logic gate for each elementary memory in the memory word. In operation, the circuit allows for individual correction of mis-programmed cells within the memory by comparing the actual contents of the memory with the desired contents. If the actual contents does not match the desired contents, that individual cell is re-programmed.

摘要翻译： 公开了一种用于在非易失性存储器中选择性地编程单个位的电路。 电路由至少一个比较器，至少一个晶体管和至少一个逻辑门组成，用于存储器字中的每个基本存储器。 在操作中，电路允许通过将存储器的实际内容与期望的内容进行比较来对存储器内的错误编程的单元进行单独校正。 如果实际内容与所需内容不匹配，那么该单个单元格将被重新编程。