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公开(公告)号:US20220385033A1
公开(公告)日:2022-12-01
申请号:US17445786
申请日:2021-08-24
发明人: Wei SHI , Hao HUANG , Siu Kwan CHEUNG , Huanlin ZHU , Lijun ZHU
IPC分类号: H01S5/024 , H01L23/373 , H01L23/498 , H01S5/02315
摘要: A substrate may include a thermally conductive metal core having a top side and a bottom side, a first dielectric coating on the top side of the metal core, a second dielectric coating on the bottom side of the metal core, a first metal circuit layer formed above the first dielectric coating, and a second metal circuit layer formed under the second dielectric coating. In some implementations, the first dielectric coating and the second dielectric coating have thicknesses below sixty micrometers and respective thermal resistances under fifteen degrees Celsius per watt. In some implementations, one or more electrical currents flowing vertically across a dielectric coating have a low parasitic inductance based on the thickness of the dielectric coating, and the metal core may dissipate heat flowing across the dielectric coating and into the metal core.
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公开(公告)号:US20220385039A1
公开(公告)日:2022-12-01
申请号:US17445787
申请日:2021-08-24
发明人: Wei SHI , Hao HUANG , Siu Kwan CHEUNG , Huanlin ZHU , Lijun ZHU
IPC分类号: H01S5/183 , G01S7/4865 , G01S17/894 , H01S5/028
摘要: A circuit (e.g., for use in a time-of-flight camera projector module) may include a top metal layer having an anode and a cathode, one or more capacitors connected to the anode, a vertical-cavity surface-emitting laser connected to the anode and the cathode, and a driver connected to the cathode. The circuit may further include a bottom metal layer connected to ground and arranged below the top metal layer, and a dielectric layer separating the top metal layer and the bottom metal layer. In some implementations, the dielectric layer has a thickness under sixty micrometers and a thermal resistance under fifteen degrees Celsius per watt. Accordingly, a current loop flowing vertically across the dielectric layer has a low self-inductance based on the thickness of the dielectric layer and the bottom metal layer is arranged to dissipate heat generated by the current loop flowing vertically across the dielectric layer.
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公开(公告)号:US20240195153A1
公开(公告)日:2024-06-13
申请号:US18194156
申请日:2023-03-31
发明人: Wei SHI , Joseph LEIGH , Suhit Ranjan DAS , Huanlin ZHU , Raman SRINIVASAN , Gianluca BACCHIN , Yuefa LI , Jacob U. LOPEZ RUVALCABA , Lijun ZHU , Qianhuan YU
IPC分类号: H01S5/42 , H01S5/0234 , H01S5/0237 , H01S5/024 , H01S5/183
CPC分类号: H01S5/423 , H01S5/0234 , H01S5/0237 , H01S5/02469 , H01S5/18305
摘要: In some implementations, an emitter assembly includes a vertical cavity surface emitting laser (VCSEL) chip including a plurality of VCSELs in a bottom-emitting configuration, and multiple VCSELs, of the plurality of VCSELs, may be grouped in a cluster. The emitter assembly may include a carrier, and the VCSEL chip may be in a flip chip configuration with the carrier. The emitter assembly may include a conductive pillar electrically connected to the multiple VCSELs grouped in the cluster.
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公开(公告)号:US20220066036A1
公开(公告)日:2022-03-03
申请号:US17109943
申请日:2020-12-02
发明人: Wei SHI , Huanlin ZHU , Lijun ZHU , Raman SRINIVASAN , Ed Murphy
IPC分类号: G01S17/89 , H01S5/183 , H05K9/00 , G01S7/4865 , G03B17/02
摘要: In some implementations, a housing for an electro-optical device comprises a molded dielectric structural component, an electromagnetic interference (EMI) shield, and a plurality of conductive traces. The molded dielectric structural component may be configured to separate the EMI shield and the plurality of conductive traces.
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公开(公告)号:US20240195152A1
公开(公告)日:2024-06-13
申请号:US18194143
申请日:2023-03-31
发明人: Wei SHI , Joseph LEIGH , Suhit Ranjan DAS , Huanlin ZHU , Raman SRINIVASAN , Gianluca BACCHIN , Yuefa LI , Jacob U. LOPEZ RUVALCABA , Lijun ZHU , Qianhuan YU
IPC分类号: H01S5/42 , H01S5/0234 , H01S5/0237
CPC分类号: H01S5/423 , H01S5/0234 , H01S5/0237
摘要: In some implementations, an emitter assembly includes a vertical cavity surface emitting laser (VCSEL) chip including a plurality of VCSELs. The emitter assembly may include a plurality of conductive pillars electrically connected to the VCSEL chip, and a conductive pillar, of the plurality of conductive pillars, may have a solder cap at an end of the conductive pillar. The emitter assembly may include a pin extending into the solder cap.
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公开(公告)号:US20220209494A1
公开(公告)日:2022-06-30
申请号:US17301332
申请日:2021-03-31
发明人: Hao HUANG , Mikhail DOLGANOV , Huanlin ZHU , Lijun ZHU
IPC分类号: H01S5/026 , H01S5/02345 , H01S5/042 , H01S5/183 , H01S5/068
摘要: A driver circuit may include a source, a first circuit path, and a second circuit path. The a first circuit path may be connected to the source and include a first anode pad, a first set of connecting elements to connect the first anode pad to an anode of an optical load, a second anode pad that is separate from the first anode pad, a second set of connecting elements to connect the anode of the optical load to the second anode pad, and a switch. The switch being in a closed state causes current to charge the first set of connecting elements and the second set of connecting elements through the first circuit path. The switch transitioning from the closed state to the open state causes the first set of connecting elements to discharge current through the second circuit path to provide an electrical pulse to the optical load.
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公开(公告)号:US20220166187A1
公开(公告)日:2022-05-26
申请号:US17301261
申请日:2021-03-30
发明人: Wei SHI , Siu Kwan CHEUNG , Lijun ZHU , Raman SRINIVASAN , Huanlin ZHU
摘要: An optical device may include a substrate including a conductive core, a first layer stack on a first surface of the conductive core, a conductor-filled trench extending through the first layer stack to the conductive core such that the conductor-filled trench is on the first surface of the conductive core, and a second layer stack on a second surface of the conductive core. The optical device may include a vertical-cavity surface-emitting laser (VCSEL) chip above the conductor-filled trench. The VCSEL chip may include an array of VCSELs. A size of the conductor-filled trench may match a size of the VCSEL chip, match a size of an emission region of the array of VCSELs, or be greater than the size of the emission region of the array of VCSELs and less than the size of the VCSEL chip.
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公开(公告)号:US20240195151A1
公开(公告)日:2024-06-13
申请号:US18194133
申请日:2023-03-31
发明人: Wei SHI , Joseph LEIGH , Suhit Ranjan DAS , Huanlin ZHU , Raman SRINIVASAN , Gianluca BACCHIN , Yuefa LI , Jacob U. LOPEZ RUVALCABA , Lijun ZHU , Qianhuan YU
IPC分类号: H01S5/42 , H01S5/0234 , H01S5/0237
CPC分类号: H01S5/423 , H01S5/0234 , H01S5/0237
摘要: In some implementations, an emitter assembly includes a vertical cavity surface emitting laser (VCSEL) chip including a plurality of VCSELs. The emitter assembly may include a plurality of conductive pillars electrically connected to the VCSEL chip. The emitter assembly may include a dummy pillar, electrically isolated from the VCSEL chip, mating with a slot. The VCSEL chip may include one of the dummy pillar or the slot.
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公开(公告)号:US20240195145A1
公开(公告)日:2024-06-13
申请号:US18194123
申请日:2023-03-31
发明人: Wei SHI , Joseph LEIGH , Eric R. HEGBLOM , Suhit Ranjan DAS , Huanlin ZHU , Raman SRINIVASAN , Gianluca BACCHIN , Yuefa LI , Jacob U. LOPEZ RUVALCABA , Lijun ZHU , Qianhuan YU
IPC分类号: H01S5/0239 , H01S5/0234 , H01S5/0237 , H01S5/02375 , H01S5/183 , H01S5/42
CPC分类号: H01S5/0239 , H01S5/0234 , H01S5/0237 , H01S5/02375 , H01S5/18305 , H01S5/423
摘要: In some implementations, an emitter assembly includes a vertical cavity surface emitting laser (VCSEL) chip including a plurality of VCSELs respectively associated with a plurality of first electrical contacts. A first spacing of the plurality of first electrical contacts may define a first pitch. The emitter assembly may include a redistribution layer, disposed on the VCSEL chip, to increase the first pitch of the plurality of first electrical contacts. The emitter assembly may include a carrier having a plurality of second electrical contacts. A second spacing of the plurality of second electrical contacts may define a second pitch greater than the first pitch. The emitter assembly may include a plurality of conductive pillars that electrically connect the plurality of first electrical contacts and the plurality of second electrical contacts via the redistribution layer. The plurality of conductive pillars may be arranged according to the second spacing.
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公开(公告)号:US20230047740A1
公开(公告)日:2023-02-16
申请号:US17449612
申请日:2021-09-30
发明人: Siu Kwan CHEUNG , Wei SHI , Hao HUANG , Lijun ZHU , Huanlin ZHU
摘要: In some implementations, a vertical cavity surface emitting laser (VCSEL) package may include a substrate. The VCSEL package may include a VCSEL disposed on a surface of the substrate. The VCSEL package may include a VCSEL driver disposed on the surface of the substrate. The VCSEL package may include an embedded capacitor electrically connected to the VCSEL and the VCSEL driver. The embedded capacitor may be formed from a subset of layers of the substrate. The capacitor may be associated with a first capacitance that is different from a second capacitance of at least one other capacitor associated with the substrate.
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