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    OPTICAL DEVICE INCLUDING A SUBSTRATE WITH A CONDUCTOR-FILLED TRENCH ON A CONDUCTIVE CORE
    3.
    发明申请
    OPTICAL DEVICE INCLUDING A SUBSTRATE WITH A CONDUCTOR-FILLED TRENCH ON A CONDUCTIVE CORE 有权

    公开(公告)号：US20220166187A1

    公开(公告)日：2022-05-26

    申请号：US17301261

    申请日：2021-03-30

    Applicant: Lumentum Operations LLC

    Inventor： Wei SHI ,  Siu Kwan CHEUNG ,  Lijun ZHU ,  Raman SRINIVASAN ,  Huanlin ZHU

    IPC: H01S5/024 ,  H01S5/183

    Abstract: An optical device may include a substrate including a conductive core, a first layer stack on a first surface of the conductive core, a conductor-filled trench extending through the first layer stack to the conductive core such that the conductor-filled trench is on the first surface of the conductive core, and a second layer stack on a second surface of the conductive core. The optical device may include a vertical-cavity surface-emitting laser (VCSEL) chip above the conductor-filled trench. The VCSEL chip may include an array of VCSELs. A size of the conductor-filled trench may match a size of the VCSEL chip, match a size of an emission region of the array of VCSELs, or be greater than the size of the emission region of the array of VCSELs and less than the size of the VCSEL chip.

    PACKAGING SUBSTRATE WITH LOW THERMAL RESISTANCE AND LOW PARASITIC INDUCTANCE
    4.
    发明申请
    PACKAGING SUBSTRATE WITH LOW THERMAL RESISTANCE AND LOW PARASITIC INDUCTANCE 有权

    公开(公告)号：US20220385033A1

    公开(公告)日：2022-12-01

    申请号：US17445786

    申请日：2021-08-24

    Applicant: Lumentum Operations LLC

    Inventor： Wei SHI ,  Hao HUANG ,  Siu Kwan CHEUNG ,  Huanlin ZHU ,  Lijun ZHU

    IPC: H01S5/024 ,  H01L23/373 ,  H01L23/498 ,  H01S5/02315

    Abstract: A substrate may include a thermally conductive metal core having a top side and a bottom side, a first dielectric coating on the top side of the metal core, a second dielectric coating on the bottom side of the metal core, a first metal circuit layer formed above the first dielectric coating, and a second metal circuit layer formed under the second dielectric coating. In some implementations, the first dielectric coating and the second dielectric coating have thicknesses below sixty micrometers and respective thermal resistances under fifteen degrees Celsius per watt. In some implementations, one or more electrical currents flowing vertically across a dielectric coating have a low parasitic inductance based on the thickness of the dielectric coating, and the metal core may dissipate heat flowing across the dielectric coating and into the metal core.

    SUBSTRATE DESIGNS FOR TIME-OF-FLIGHT CAMERA PROJECTORS WITH LOW THERMAL RESISTANCE AND LOW PARASITIC INDUCTANCE
    6.
    发明申请
    SUBSTRATE DESIGNS FOR TIME-OF-FLIGHT CAMERA PROJECTORS WITH LOW THERMAL RESISTANCE AND LOW PARASITIC INDUCTANCE 有权

    公开(公告)号：US20220385039A1

    公开(公告)日：2022-12-01

    申请号：US17445787

    申请日：2021-08-24

    Applicant: Lumentum Operations LLC

    Inventor： Wei SHI ,  Hao HUANG ,  Siu Kwan CHEUNG ,  Huanlin ZHU ,  Lijun ZHU

    IPC: H01S5/183 ,  G01S7/4865 ,  G01S17/894 ,  H01S5/028

    Abstract: A circuit (e.g., for use in a time-of-flight camera projector module) may include a top metal layer having an anode and a cathode, one or more capacitors connected to the anode, a vertical-cavity surface-emitting laser connected to the anode and the cathode, and a driver connected to the cathode. The circuit may further include a bottom metal layer connected to ground and arranged below the top metal layer, and a dielectric layer separating the top metal layer and the bottom metal layer. In some implementations, the dielectric layer has a thickness under sixty micrometers and a thermal resistance under fifteen degrees Celsius per watt. Accordingly, a current loop flowing vertically across the dielectric layer has a low self-inductance based on the thickness of the dielectric layer and the bottom metal layer is arranged to dissipate heat generated by the current loop flowing vertically across the dielectric layer.

    ELECTRODE BRIDGING IN AN EMITTER ASSEMBLY
    7.
    发明申请
    ELECTRODE BRIDGING IN AN EMITTER ASSEMBLY 有权

    公开(公告)号：US20240396297A1

    公开(公告)日：2024-11-28

    申请号：US18362569

    申请日：2023-07-31

    Applicant: Lumentum Operations LLC

    Inventor： Siu Kwan CHEUNG ,  Lijun ZHU ,  Qianhuan YU ,  Benjamin KESLER ,  Wei SHI ,  Joseph LEIGH

    IPC: H01S5/042 ,  H01S5/42

    Abstract: In some implementations, an emitter assembly includes a vertical cavity surface emitting laser (VCSEL) device. The VCSEL device may include a substrate. The VCSEL device may include a plurality of VCSELs on the substrate. The VCSEL device may include at least one anode layer on the substrate and electrically connected to the plurality of VCSELs. The VCSEL device may include a cathode electrode over at least a portion of multiple VCSELs, of the plurality of VCSELs, and electrically connected to the multiple VCSELs. The cathode electrode may include multiple cathode electrode fingers. The emitter assembly may include a bridge element that electrically connects a first finger of the multiple cathode electrode fingers and a second finger of the multiple cathode electrode fingers.

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