Method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems

    公开(公告)号:US10302880B2

    公开(公告)日:2019-05-28

    申请号:US16110587

    申请日:2018-08-23

    Applicant: Luxtera, Inc.

    Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

    Method And System For Implementing High-Speed Electrical Interfaces Between Semiconductor Dies In Optical Communication Systems

    公开(公告)号:US20190293883A1

    公开(公告)日:2019-09-26

    申请号:US16424136

    申请日:2019-05-28

    Applicant: Luxtera, Inc.

    Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

    Method And System For Encoding Multi-Level Pulse Amplitude Modulated Signals Using Integrated Optoelectronic Devices

    公开(公告)号:US20190296830A1

    公开(公告)日:2019-09-26

    申请号:US16424137

    申请日:2019-05-28

    Applicant: Luxtera, Inc.

    Abstract: Methods and systems for encoding multi-level pulse amplitude modulated signals using integrated optoelectronics are disclosed and may include generating a multi-level, amplitude-modulated optical signal utilizing an optical modulator driven by first and second electrical input signals, where the optical modulator may configure levels in the multi-level amplitude modulated optical signal, drivers are coupled to the optical modulator; and the first and second electrical input signals may be synchronized before being communicated to the drivers. The optical modulator may include optical modulator elements coupled in series and configured into groups. The number of optical modular elements and groups may configure the number of levels in the multi-level amplitude modulated optical signal. Unit drivers may be coupled to each of the groups. The electrical input signals may be synchronized before communicating them to the unit drivers utilizing flip-flops. Phase addition may be synchronized utilizing one or more electrical delay lines.

    Method and system for optoelectronics transceivers integrated on a CMOS chip

    公开(公告)号:US10341021B2

    公开(公告)日:2019-07-02

    申请号:US15804680

    申请日:2017-11-06

    Applicant: Luxtera, Inc.

    Abstract: Methods and systems for optoelectronics transceivers integrated on a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers on a top surface of a CMOS chip, which may include a guard ring. Photodetectors may be integrated in the CMOS chip. A CW optical signal may be received from a laser source via optical couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the top surface of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser.

    Method and system for encoding multi-level pulse amplitude modulated signals using integrated optoelectronic devices

    公开(公告)号:US10305597B2

    公开(公告)日:2019-05-28

    申请号:US15407440

    申请日:2017-01-17

    Applicant: Luxtera, Inc.

    Abstract: Methods and systems for encoding multi-level pulse amplitude modulated signals using integrated optoelectronics are disclosed and may include generating a multi-level, amplitude-modulated optical signal utilizing an optical modulator driven by first and second electrical input signals, where the optical modulator may configure levels in the multi-level amplitude modulated optical signal, drivers are coupled to the optical modulator; and the first and second electrical input signals may be synchronized before being communicated to the drivers. The optical modulator may include optical modulator elements coupled in series and configured into groups. The number of optical modular elements and groups may configure the number of levels in the multi-level amplitude modulated optical signal. Unit drivers may be coupled to each of the groups. The electrical input signals may be synchronized before communicating them to the unit drivers utilizing flip-flops. Phase addition may be synchronized utilizing one or more electrical delay lines.

    Method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems

    公开(公告)号:US10061094B2

    公开(公告)日:2018-08-28

    申请号:US15716103

    申请日:2017-09-26

    Applicant: Luxtera, Inc.

    Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

    Method And System For Implementing High-Speed Electrical Interfaces Between Semiconductor Dies in Optical Communication Systems

    公开(公告)号:US20180017747A1

    公开(公告)日:2018-01-18

    申请号:US15716103

    申请日:2017-09-26

    Applicant: Luxtera, Inc.

    CPC classification number: G02B6/4274 G02B6/4286

    Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Patent Agency Ranking