公开(公告)号：US06885043B2

公开(公告)日：2005-04-26

申请号：US10051237

申请日：2002-01-18

申请人： Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

发明人： Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

IPC分类号： H01L27/118 ,  H01I29/739

CPC分类号： H01L27/118

摘要： An embodiment of the invention includes a routing architecture with a plurality of predesigned layers and a custom layer. The structure includes a plurality of parallel vertical tracks. In one layer, the tracks include a pin coupled to an input/output of an underlying function block and the track also includes a first portion of an unbroken conductive path. A second portion of the unbroken conductive path is formed under the pin in at least a second predesigned layer. In some embodiments, the second portion of the unbroken conductive path is formed in the second predesigned layer for some tracks and a third predesigned layer for other tracks. Hence, pins and unbroken conductive paths are multiplexed in a single track. In addition, the second predesigned layer further includes long horizontal conductors. When using the predesigned layers, the custom layer can be structured to provide free global routing with distinct local routing, all while using an array structure independent of routing channels and without rendering any function blocks unusable. Moreover, a structure in accordance with the invention includes conductors for clock distribution which can be used to form multiple independent clock domains. The structure is compact, yet flexible and can be customized in some embodiments with 1-2 masks.

摘要翻译： 本发明的实施例包括具有多个预先设计的层和定制层的路由架构。 该结构包括多个平行的垂直轨道。 在一个层中，轨迹包括一个与底层功能块的输入/输出相连的引脚，并且轨道还包括不间断导电路径的第一部分。 不间断导电路径的第二部分在至少第二预设计层中形成在引脚下方。 在一些实施例中，不间断导电路径的第二部分形成在用于一些轨道的第二预设计层中，以及用于其它轨道的第三预设计层。 因此，引脚和不间断的导电路径被复用在单个轨道中。 此外，第二预先设计的层还包括长的水平导体。 当使用预先设计的图层时，自定义图层可以被构造为提供具有不同本地路由的免费全局路由，同时使用独立于路由通道的阵列结构，并且不会使任何功能块不可用。 此外，根据本发明的结构包括可用于形成多个独立时钟域的用于时钟分配的导体。 该结构紧凑而又灵活，并且可以在具有1-2个掩模的一些实施例中进行定制。

公开(公告)号：US06696856B1

公开(公告)日：2004-02-24

申请号：US10020469

申请日：2001-10-30

申请人： Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

发明人： Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

IPC分类号： G06F738

CPC分类号： H03K19/1736

摘要： Described herein is an ASIC having an array of predesigned function blocks. The function blocks can be used to implement combinational logic, sequential logic, or a combination of both. The function blocks also have a selectable output drive strength. The output drive strength can be selected, in some embodiments, using mask programming.

摘要翻译： 这里描述的是具有预先设计的功能块阵列的ASIC。 功能块可用于实现组合逻辑，顺序逻辑或两者的组合。 功能块也具有可选的输出驱动强度。 在一些实施例中，可以使用掩模编程来选择输出驱动强度。

公开(公告)号：US06769109B2

公开(公告)日：2004-07-27

申请号：US09877170

申请日：2001-06-08

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

IPC分类号： G06F1750

CPC分类号： H03K19/17708 ,  H01L27/118

摘要： In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

公开(公告)号：US06694491B1

公开(公告)日：2004-02-17

申请号：US09512783

申请日：2000-02-25

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

IPC分类号： G06F1750

CPC分类号： H01L27/118

摘要： In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

摘要翻译： 根据本发明，公开了一种用于定制一次性可配置集成电路以包括多时间可配置结构的方法。 这种方法包括，在一个实施例中，从用户接收电路功能的描述以在一次性可配置设备中实现，其中功能包括由用户指定为可重新配置的部分。 然后，根据本发明的实施例的方法对具有足够容量以容纳指定功能的可重构结构进行建模。 可选地，本发明的一些实施例增加了比实现指定功能所需的容量更多的容量以允许将来的重新编程。 该方法然后将可重构结构嵌入在一次性可配置设备中。 在某些实施例中，一次性可配置设备可以是掩模编程的MBA，门阵列或标准单元，而可重构结构是PLA或修改的PLA。

公开(公告)号：US07043713B2

公开(公告)日：2006-05-09

申请号：US10640171

申请日：2003-08-12

申请人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

发明人： Robert Osann, Jr. ,  Shafy Eltoukhy ,  Shridhar Mukund ,  Lyle Smith

IPC分类号： G06F17/50

CPC分类号： H03K19/17708 ,  H01L27/118

摘要： In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.

摘要翻译： 根据本发明，公开了一种用于定制一次性可配置集成电路以包括多时间可配置结构的方法。 这种方法包括，在一个实施例中，从用户接收电路功能的描述以在一次性可配置设备中实现，其中功能包括由用户指定为可重新配置的部分。 然后，根据本发明的实施例的方法对具有足够容量以容纳指定功能的可重构结构进行建模。 可选地，本发明的一些实施例增加了比实现指定功能所需的容量更多的容量以允许将来的重新编程。 该方法然后将可重构结构嵌入在一次性可配置设备中。 在某些实施例中，一次性可配置设备可以是掩模编程的MBA，门阵列或标准单元，而可重构结构是PLA或修改的PLA。

公开(公告)号：US06861867B2

公开(公告)日：2005-03-01

申请号：US10093767

申请日：2002-03-07

申请人： Eric West ,  Shridhar Mukund

发明人： Eric West ,  Shridhar Mukund

IPC分类号： G01R31/3185 ,  G06F7/38 ,  G01R31/28

CPC分类号： G01R31/318516 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/318594

摘要： A system for remotely/automatedly testing an ASIC and particularly to testing a user-designed circuit is disclosed. In general, a system in accordance with the invention includes a plurality of cells, where the cells are couplable to form a user-designed circuit, e.g., by customizing routing. Within the ASIC and prior to any knowledge of the user-designed circuit, the ASIC includes circuitry to enable internal remote/automated testing of the user-designed circuit to be later formed. The circuitry controls the input and mode of operation of the cells and the sequencing of multiple synchronous or asynchronous clock domain inputs thereby providing testing of the user-designed circuit at speed for stuck-at-faults and delay faults.

摘要翻译： 公开了用于远程/自动测试ASIC的系统，特别是用于测试用户设计的电路的系统。 通常，根据本发明的系统包括多个单元，其中单元可耦合以形成用户设计的电路，例如通过定制路由。 在ASIC内，并且在用户设计的电路的任何知识之前，ASIC包括用于使用户稍后形成的用户设计电路的内部远程/自动测试的电路。 电路控制单元的输入和操作模式以及多个同步或异步时钟域输入的排序，从而以卡通故障和延迟故障的速度提供用户设计电路的测试。

公开(公告)号：US07849441B2

公开(公告)日：2010-12-07

申请号：US11426882

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

发明人： Shridhar Mukund ,  Anjan Mitra ,  Jed Krohnfeldt ,  Clement Leung

IPC分类号： G06F9/44

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

摘要翻译： 提供了一种用于指定有状态的，面向事务的系统的方法。 该方法通过指定多个原始FlowModules来启动。 该方法包括在多个FlowModules中的每一个中定义至少一个FlowGate，其中每个FlowGate包括不可中断的过程代码序列，单个入口点，并由命名的并发调用进行调用。 从调用FlowGate指定一个Arc到被称为FlowGate的Arc，并且为被调用的FlowGate的每个命名调用生成一个Signal。 定义一个通道用于携带信号。 提供了用于在半导体器件中合成半导体器件和路由信号的方法。

公开(公告)号：US07320013B2

公开(公告)日：2008-01-15

申请号：US10726427

申请日：2003-12-02

申请人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

发明人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

IPC分类号： G06F5/01

CPC分类号： G06F5/01 ,  G06F7/49994

摘要： A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second operand has a greater bit width than the first operand. Next, the first operand is transformed by aligning a least significant bit of the first operand to a lowest bit position of a transformed operand having a bit size equal to the second operand. Then, the bits of the transformed operand are sign extended and padded in a manner to allow carry propagation. Next, the transformed operand is transmitted to the processor. A method for shifting operands and a processor are also provided.

摘要翻译： 提供了一种透明地呈现不同大小的待处理操作数的方法。 该方法通过提供具有第一位宽的第一操作数来启动。 然后，确定与处理器相关联的第二操作数的位宽度。 第二个操作数的位宽比第一个操作数大。 接下来，通过将第一操作数的最低有效位与具有等于第二操作数的位大小的变换操作数的最低位位置对齐来变换第一操作数。 然后，变换的操作数的位被符号扩展并以允许进位传播的方式填充。 接下来，将变换的操作数传送到处理器。 还提供了用于移位操作数和处理器的方法。

公开(公告)号：US07162630B2

公开(公告)日：2007-01-09

申请号：US10233303

申请日：2002-08-30

申请人： Todd Sperry ,  Sivakumar Munnangi ,  Shridhar Mukund

发明人： Todd Sperry ,  Sivakumar Munnangi ,  Shridhar Mukund

IPC分类号： H04L9/00 ,  H04L9/32

CPC分类号： H04L47/10 ,  H04L29/06 ,  H04L47/193 ,  H04L63/0272 ,  H04L63/0428 ,  H04L63/0485 ,  H04L63/061 ,  H04L63/08 ,  H04L63/164 ,  H04L67/06 ,  H04L67/28 ,  H04L67/2828 ,  H04L67/289 ,  H04L69/10 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163 ,  H04L69/166 ,  H04L69/22 ,  H04L69/24 ,  H04L69/329

摘要： An architecture for implementing host-based security such that data security may be applied whenever the confidential data leaves a host computer or a networked device. The improved method and architecture may be implemented in a single integrated circuit for speed, power consumption, and space-utilization reasons. Within the integrated circuit, a combination of hardware-implemented, network processor-implemented, and software-implemented functions may be provided. The innovative host-based security architecture may offer line-rate IPSec acceleration, TCP acceleration, or both.

摘要翻译： 用于实现基于主机的安全性的架构，使得每当机密数据离开主计算机或网络设备时可以应用数据安全性。 改进的方法和架构可以在单个集成电路中实现，用于速度，功率消耗和空间利用的原因。 在集成电路中，可以提供硬件实现的，网络处理器实现的和软件实现的功能的组合。 创新的基于主机的安全架构可以提供线速IPSec加速，TCP加速或两者兼容。

公开(公告)号：US06611932B2

公开(公告)日：2003-08-26

申请号：US10056686

申请日：2002-01-24

申请人： Dana How ,  Adi Srinivasan ,  Robert Osann, Jr. ,  Shridhar Mukund

发明人： Dana How ,  Adi Srinivasan ,  Robert Osann, Jr. ,  Shridhar Mukund

IPC分类号： G01R3128

CPC分类号： G01R31/318516

摘要： A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. In normal mode, a logic block can implement combinational, sequential, or other functions and still later be as a master-slave flip-flop. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage.

摘要翻译： 公开了用于测试集成电路，特别是门阵列的系统，其在耦合阵列以形成用户设计的电路之前包括能够测试用户设计的电路的预先设计的逻辑。 预先设计的逻辑允许阵列中的逻辑块以“冻结”模式运行或在正常模式下运行，其中正常模式由用户设计的电路定义。 当逻辑块被选择为冻结时，逻辑块表现为一系列菊花链主主机触发器。 在正常模式下，逻辑块可以实现组合，顺序或其他功能，并且稍后将作为主从触发器。 此外，每个逻辑块进一步配置为可寻址模式控制，允许一旦激励数据被移位，孤立地选择逻辑块，简化测试生成并提高故障覆盖。